2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
45 #include "sim/host.hh"
46 #include "base/misc.hh"
49 #include "mem/cache/cache.hh"
50 #include "mem/cache/cache_blk.hh"
51 #include "mem/cache/miss/mshr.hh"
52 #include "mem/cache/prefetch/prefetcher.hh"
54 #include "sim/sim_events.hh" // for SimExitEvent
58 template<class TagStore, class Buffering, class Coherence>
60 Cache<TagStore,Buffering,Coherence>::
61 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
69 if (pkt->isResponse())
74 return true; //Deal with blocking....
77 template<class TagStore, class Buffering, class Coherence>
79 Cache<TagStore,Buffering,Coherence>::
80 doAtomicAccess(Packet *pkt, bool isCpuSide)
88 if (pkt->isResponse())
91 snoopProbe(pkt, true);
93 //Fix this timing info
97 template<class TagStore, class Buffering, class Coherence>
99 Cache<TagStore,Buffering,Coherence>::
100 doFunctionalAccess(Packet *pkt, bool isCpuSide)
108 if (pkt->isResponse())
111 snoopProbe(pkt, true);
115 template<class TagStore, class Buffering, class Coherence>
117 Cache<TagStore,Buffering,Coherence>::
118 recvStatusChange(Port::Status status, bool isCpuSide)
124 template<class TagStore, class Buffering, class Coherence>
125 Cache<TagStore,Buffering,Coherence>::
126 Cache(const std::string &_name,
127 Cache<TagStore,Buffering,Coherence>::Params ¶ms)
128 : BaseCache(_name, params.baseParams),
129 prefetchAccess(params.prefetchAccess),
130 tags(params.tags), missQueue(params.missQueue),
131 coherence(params.coherence), prefetcher(params.prefetcher),
132 doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
135 // if (params.in == NULL) {
136 topLevelCache = true;
138 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
139 tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
140 tags->setPrefetcher(prefetcher);
141 missQueue->setCache(this);
142 missQueue->setPrefetcher(prefetcher);
143 coherence->setCache(this);
144 prefetcher->setCache(this);
145 prefetcher->setTags(tags);
146 prefetcher->setBuffer(missQueue);
148 invalidatePkt = new Packet;
149 invalidatePkt->cmd = Packet::InvalidateReq;
153 template<class TagStore, class Buffering, class Coherence>
155 Cache<TagStore,Buffering,Coherence>::regStats()
157 BaseCache::regStats();
158 tags->regStats(name());
159 missQueue->regStats(name());
160 coherence->regStats(name());
161 prefetcher->regStats(name());
164 template<class TagStore, class Buffering, class Coherence>
166 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
168 //@todo Add back in MemDebug Calls
169 // MemDebug::cacheAccess(pkt);
171 PacketList writebacks;
173 int lat = hitLatency;
174 if (prefetchAccess) {
175 //We are determining prefetches on access stream, call prefetcher
176 prefetcher->handleMiss(pkt, curTick);
178 if (!pkt->req->isUncacheable()) {
179 if (pkt->isInvalidate() && !pkt->isRead()
180 && !pkt->isWrite()) {
181 //Upgrade or Invalidate
182 //Look into what happens if two slave caches on bus
183 DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
184 pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1),
185 pkt->getAddr() & ~((Addr)blkSize - 1));
187 //@todo Should this return latency have the hit latency in it?
188 // respond(pkt,curTick+lat);
189 pkt->flags |= SATISFIED;
190 // return MA_HIT; //@todo, return values
193 blk = tags->handleAccess(pkt, lat, writebacks);
195 size = pkt->getSize();
197 // If this is a block size write/hint (WH64) allocate the block here
198 // if the coherence protocol allows it.
199 /** @todo make the fast write alloc (wh64) work with coherence. */
200 /** @todo Do we want to do fast writes for writebacks as well? */
201 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
202 (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
203 // not outstanding misses, can do this
204 MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr(), pkt->req->getAsid());
205 if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
206 if (outstanding_miss) {
207 warn("WriteInv doing a fastallocate"
208 "with an outstanding miss to the same address\n");
210 blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
215 while (!writebacks.empty()) {
216 missQueue->doWriteback(writebacks.front());
217 writebacks.pop_front();
219 DPRINTF(Cache, "%s %d %x %s blk_addr: %x pc %x\n", pkt->cmdString(),
220 pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
221 pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC());
224 hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
225 // clear dirty bit if write through
226 if (pkt->needsResponse())
227 respond(pkt, curTick+lat);
233 if (!pkt->req->isUncacheable()) {
234 misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
235 /** @todo Move miss count code into BaseCache */
239 new SimLoopExitEvent(curTick, "A cache reached the maximum miss count");
242 missQueue->handleMiss(pkt, size, curTick + hitLatency);
243 // return MA_CACHE_MISS;
248 template<class TagStore, class Buffering, class Coherence>
250 Cache<TagStore,Buffering,Coherence>::getPacket()
252 Packet * pkt = missQueue->getPacket();
254 if (!pkt->req->isUncacheable()) {
255 if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][pkt->req->getThreadNum()]++;
256 BlkType *blk = tags->findBlock(pkt);
257 Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
258 (blk)? blk->status : 0);
259 missQueue->setBusCmd(pkt, cmd);
263 assert(!doMasterRequest() || missQueue->havePending());
264 assert(!pkt || pkt->time <= curTick);
268 template<class TagStore, class Buffering, class Coherence>
270 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, bool success)
273 missQueue->markInService(pkt);
274 //Temp Hack for UPGRADES
275 if (pkt->cmd == Packet::UpgradeReq) {
278 } else if (pkt && !pkt->req->isUncacheable()) {
279 missQueue->restoreOrigCmd(pkt);
283 template<class TagStore, class Buffering, class Coherence>
285 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
288 if (pkt->senderState) {
289 // MemDebug::cacheResponse(pkt);
290 DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
291 pkt->getAddr() & (((ULL(1))<<48)-1));
293 if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
294 blk = tags->findBlock(pkt);
295 CacheBlk::State old_state = (blk) ? blk->status : 0;
296 PacketList writebacks;
297 blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
298 coherence->getNewState(pkt,old_state),
300 while (!writebacks.empty()) {
301 missQueue->doWriteback(writebacks.front());
304 missQueue->handleResponse(pkt, curTick + hitLatency);
308 template<class TagStore, class Buffering, class Coherence>
310 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr, int asid)
312 // Need to temporarily move this blk into MSHRs
313 MSHR *mshr = missQueue->allocateTargetList(addr, asid);
316 // Read the data into the mshr
317 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
318 assert(dummy.empty());
319 assert(mshr->pkt->flags & SATISFIED);
320 // can overload order since it isn't used on non pending blocks
321 mshr->order = blk->status;
322 // temporarily remove the block from the cache.
323 tags->invalidateBlk(addr, asid);
326 template<class TagStore, class Buffering, class Coherence>
328 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
330 // Need to temporarily move this blk into MSHRs
331 assert(mshr->pkt->cmd == Packet::ReadReq);
334 // Read the data into the mshr
335 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
336 assert(dummy.empty());
337 assert(mshr->pkt->flags & SATISFIED);
338 // can overload order since it isn't used on non pending blocks
339 mshr->order = blk->status;
340 // temporarily remove the block from the cache.
341 tags->invalidateBlk(mshr->pkt->getAddr(), mshr->pkt->req->getAsid());
345 template<class TagStore, class Buffering, class Coherence>
347 Cache<TagStore,Buffering,Coherence>::getCoherenceReq()
349 return coherence->getPacket();
353 template<class TagStore, class Buffering, class Coherence>
355 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
358 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
359 BlkType *blk = tags->findBlock(pkt);
360 MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
361 if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
362 //If we find an mshr, and it is in service, we need to NACK or invalidate
364 if (mshr->inService) {
365 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
366 && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
367 //If the outstanding request was an invalidate (upgrade,readex,..)
368 //Then we need to ACK the request until we get the data
369 //Also NACK if the outstanding request is not a cachefill (writeback)
370 pkt->flags |= NACKED_LINE;
374 //The supplier will be someone else, because we are waiting for
375 //the data. This should cause this cache to be forced to go to
376 //the shared state, not the exclusive even though the shared line
377 //won't be asserted. But for now we will just invlidate ourselves
378 //and allow the other cache to go into the exclusive state.
379 //@todo Make it so a read to a pending read doesn't invalidate.
380 //@todo Make it so that a read to a pending read can't be exclusive now.
382 //Set the address so find match works
383 invalidatePkt->addrOverride(pkt->getAddr());
385 //Append the invalidate on
386 missQueue->addTarget(mshr,invalidatePkt);
387 DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
392 //We also need to check the writeback buffers and handle those
393 std::vector<MSHR *> writebacks;
394 if (missQueue->findWrites(blk_addr, pkt->req->getAsid(), writebacks)) {
395 DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
397 //Look through writebacks for any non-uncachable writes, use that
398 for (int i=0; i<writebacks.size(); i++) {
399 mshr = writebacks[i];
401 if (!mshr->pkt->req->isUncacheable()) {
403 //Only Upgrades don't get here
405 pkt->flags |= SATISFIED;
407 //If we are in an exclusive protocol, make it ask again
408 //to get write permissions (upgrade), signal shared
409 pkt->flags |= SHARED_LINE;
411 assert(pkt->isRead());
412 Addr offset = pkt->getAddr() & ~(blkSize - 1);
413 assert(offset < blkSize);
414 assert(pkt->getSize() <= blkSize);
415 assert(offset + pkt->getSize() <=blkSize);
416 memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
421 if (pkt->isInvalidate()) {
422 //This must be an upgrade or other cache will take ownership
423 missQueue->markInService(mshr->pkt);
430 CacheBlk::State new_state;
431 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
433 tags->handleSnoop(blk, new_state, pkt);
437 tags->handleSnoop(blk, new_state);
440 template<class TagStore, class Buffering, class Coherence>
442 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
444 //Need to handle the response, if NACKED
445 if (pkt->flags & NACKED_LINE) {
446 //Need to mark it as not in service, and retry for bus
447 assert(0); //Yeah, we saw a NACK come through
449 //For now this should never get called, we return false when we see a NACK
450 //instead, by doing this we allow the bus_blocked mechanism to handle the retry
451 //For now it retrys in just 2 cycles, need to figure out how to change that
452 //Eventually we will want to also have success come in as a parameter
453 //Need to make sure that we handle the functionality that happens on successufl
454 //return of the sendAddr function
458 template<class TagStore, class Buffering, class Coherence>
460 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr, int asid)
462 tags->invalidateBlk(addr,asid);
467 * @todo Fix to not assume write allocate
469 template<class TagStore, class Buffering, class Coherence>
471 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
473 // MemDebug::cacheProbe(pkt);
474 if (!pkt->req->isUncacheable()) {
475 if (pkt->isInvalidate() && !pkt->isRead()
476 && !pkt->isWrite()) {
477 //Upgrade or Invalidate, satisfy it, don't forward
478 DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
479 pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1),
480 pkt->getAddr() & ~((Addr)blkSize - 1));
481 pkt->flags |= SATISFIED;
486 PacketList writebacks;
488 BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
491 // Need to check for outstanding misses and writes
492 Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
494 // There can only be one matching outstanding miss.
495 MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
497 // There can be many matching outstanding writes.
498 vector<MSHR*> writes;
499 missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
502 memSidePort->sendFunctional(pkt);
503 // Check for data in MSHR and writebuffer.
505 warn("Found outstanding miss on an non-update probe");
506 MSHR::TargetList *targets = mshr->getTargetList();
507 MSHR::TargetList::iterator i = targets->begin();
508 MSHR::TargetList::iterator end = targets->end();
509 for (; i != end; ++i) {
510 Packet * target = *i;
511 // If the target contains data, and it overlaps the
512 // probed request, need to update data
513 if (target->isWrite() && target->intersect(pkt)) {
517 if (target->getAddr() < pkt->getAddr()) {
518 int offset = pkt->getAddr() - target->getAddr();
519 pkt_data = pkt->getPtr<uint8_t>();
520 write_data = target->getPtr<uint8_t>() + offset;
521 data_size = target->getSize() - offset;
522 assert(data_size > 0);
523 if (data_size > pkt->getSize())
524 data_size = pkt->getSize();
526 int offset = target->getAddr() - pkt->getAddr();
527 pkt_data = pkt->getPtr<uint8_t>() + offset;
528 write_data = target->getPtr<uint8_t>();
529 data_size = pkt->getSize() - offset;
530 assert(data_size > pkt->getSize());
531 if (data_size > target->getSize())
532 data_size = target->getSize();
535 if (pkt->isWrite()) {
536 memcpy(pkt_data, write_data, data_size);
538 memcpy(write_data, pkt_data, data_size);
543 for (int i = 0; i < writes.size(); ++i) {
544 Packet * write = writes[i]->pkt;
545 if (write->intersect(pkt)) {
546 warn("Found outstanding write on an non-update probe");
550 if (write->getAddr() < pkt->getAddr()) {
551 int offset = pkt->getAddr() - write->getAddr();
552 pkt_data = pkt->getPtr<uint8_t>();
553 write_data = write->getPtr<uint8_t>() + offset;
554 data_size = write->getSize() - offset;
555 assert(data_size > 0);
556 if (data_size > pkt->getSize())
557 data_size = pkt->getSize();
559 int offset = write->getAddr() - pkt->getAddr();
560 pkt_data = pkt->getPtr<uint8_t>() + offset;
561 write_data = write->getPtr<uint8_t>();
562 data_size = pkt->getSize() - offset;
563 assert(data_size > pkt->getSize());
564 if (data_size > write->getSize())
565 data_size = write->getSize();
568 if (pkt->isWrite()) {
569 memcpy(pkt_data, write_data, data_size);
571 memcpy(write_data, pkt_data, data_size);
578 // update the cache state and statistics
579 if (mshr || !writes.empty()){
580 // Can't handle it, return pktuest unsatisfied.
583 if (!pkt->req->isUncacheable()) {
584 // Fetch the cache block to fill
585 BlkType *blk = tags->findBlock(pkt);
586 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
587 (blk)? blk->status : 0);
589 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
593 busPkt->time = curTick;
595 lat = memSidePort->sendAtomic(busPkt);
597 if (!(busPkt->flags & SATISFIED)) {
598 // blocked at a higher level, just return
602 misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
604 CacheBlk::State old_state = (blk) ? blk->status : 0;
605 tags->handleFill(blk, busPkt,
606 coherence->getNewState(busPkt, old_state),
608 // Handle writebacks if needed
609 while (!writebacks.empty()){
610 memSidePort->sendAtomic(writebacks.front());
611 writebacks.pop_front();
613 return lat + hitLatency;
615 return memSidePort->sendAtomic(pkt);
619 // There was a cache hit.
620 // Handle writebacks if needed
621 while (!writebacks.empty()){
622 memSidePort->sendAtomic(writebacks.front());
623 writebacks.pop_front();
627 hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
628 } else if (pkt->isWrite()) {
629 // Still need to change data in all locations.
630 return memSidePort->sendAtomic(pkt);
632 return curTick + lat;
634 fatal("Probe not handled.\n");
638 template<class TagStore, class Buffering, class Coherence>
640 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt, bool update)
642 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
643 BlkType *blk = tags->findBlock(pkt);
644 MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
645 CacheBlk::State new_state = 0;
646 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
648 tags->handleSnoop(blk, new_state, pkt);
651 tags->handleSnoop(blk, new_state);