src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(Packet *pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         //Temporary solution to LL/SC
  90         if (pkt->isWrite() && (pkt->req->isLocked())) {
  91             pkt->req->setScResult(1);
  92         }
  93
  94         probe(pkt, true, NULL);
  95         //TEMP ALWAYS SUCCES FOR NOW
  96         pkt->result = Packet::Success;
  97     }
  98     else
  99     {
 100         if (pkt->isResponse())
 101             handleResponse(pkt);
 102         else
 103             return snoopProbe(pkt);
 104     }
 105     //Fix this timing info
 106     return hitLatency;
 107 }
 108
 109 template<class TagStore, class Buffering, class Coherence>
 110 void
 111 Cache<TagStore,Buffering,Coherence>::
 112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 113 {
 114     if (isCpuSide)
 115     {
 116         //TEMP USE CPU?THREAD 0 0
 117         pkt->req->setThreadContext(0,0);
 118
 119         //Temporary solution to LL/SC
 120         if (pkt->isWrite() && (pkt->req->isLocked())) {
 121             assert("Can't handle LL/SC on functional path\n");
 122         }
 123
 124         probe(pkt, false, memSidePort);
 125         //TEMP ALWAYS SUCCESFUL FOR NOW
 126         pkt->result = Packet::Success;
 127     }
 128     else
 129     {
 130             probe(pkt, false, cpuSidePort);
 131     }
 132 }
 133
 134 template<class TagStore, class Buffering, class Coherence>
 135 void
 136 Cache<TagStore,Buffering,Coherence>::
 137 recvStatusChange(Port::Status status, bool isCpuSide)
 138 {
 139
 140 }
 141
 142
 143 template<class TagStore, class Buffering, class Coherence>
 144 Cache<TagStore,Buffering,Coherence>::
 145 Cache(const std::string &_name,
 146       Cache<TagStore,Buffering,Coherence>::Params &params)
 147     : BaseCache(_name, params.baseParams),
 148       prefetchAccess(params.prefetchAccess),
 149       tags(params.tags), missQueue(params.missQueue),
 150       coherence(params.coherence), prefetcher(params.prefetcher),
 151       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
 152       hitLatency(params.hitLatency)
 153 {
 154     tags->setCache(this);
 155     tags->setPrefetcher(prefetcher);
 156     missQueue->setCache(this);
 157     missQueue->setPrefetcher(prefetcher);
 158     coherence->setCache(this);
 159     prefetcher->setCache(this);
 160     prefetcher->setTags(tags);
 161     prefetcher->setBuffer(missQueue);
 162     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 163     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 164 }
 165
 166 template<class TagStore, class Buffering, class Coherence>
 167 void
 168 Cache<TagStore,Buffering,Coherence>::regStats()
 169 {
 170     BaseCache::regStats();
 171     tags->regStats(name());
 172     missQueue->regStats(name());
 173     coherence->regStats(name());
 174     prefetcher->regStats(name());
 175 }
 176
 177 template<class TagStore, class Buffering, class Coherence>
 178 bool
 179 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 180 {
 181 //@todo Add back in MemDebug Calls
 182 //    MemDebug::cacheAccess(pkt);
 183     BlkType *blk = NULL;
 184     PacketList writebacks;
 185     int size = blkSize;
 186     int lat = hitLatency;
 187     if (prefetchAccess) {
 188         //We are determining prefetches on access stream, call prefetcher
 189         prefetcher->handleMiss(pkt, curTick);
 190     }
 191     if (!pkt->req->isUncacheable()) {
 192         blk = tags->handleAccess(pkt, lat, writebacks);
 193     } else {
 194         size = pkt->getSize();
 195     }
 196     // If this is a block size write/hint (WH64) allocate the block here
 197     // if the coherence protocol allows it.
 198     /** @todo make the fast write alloc (wh64) work with coherence. */
 199     /** @todo Do we want to do fast writes for writebacks as well? */
 200     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 201         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 202         // not outstanding misses, can do this
 203         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 204         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 205             if (outstanding_miss) {
 206                 warn("WriteInv doing a fastallocate"
 207                      "with an outstanding miss to the same address\n");
 208             }
 209             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 210                                    writebacks);
 211             ++fastWrites;
 212         }
 213     }
 214     while (!writebacks.empty()) {
 215         missQueue->doWriteback(writebacks.front());
 216         writebacks.pop_front();
 217     }
 218     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 219             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 220             pkt->getAddr() & ~((Addr)blkSize - 1));
 221     if (blk) {
 222         // Hit
 223         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 224         // clear dirty bit if write through
 225         if (pkt->needsResponse())
 226             respond(pkt, curTick+lat);
 227         if (pkt->cmd == Packet::Writeback) {
 228             //Signal that you can kill the pkt/req
 229             pkt->flags |= SATISFIED;
 230         }
 231         return true;
 232     }
 233
 234     // Miss
 235     if (!pkt->req->isUncacheable()) {
 236         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 237         /** @todo Move miss count code into BaseCache */
 238         if (missCount) {
 239             --missCount;
 240             if (missCount == 0)
 241                 exitSimLoop("A cache reached the maximum miss count");
 242         }
 243     }
 244     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 245 //    return MA_CACHE_MISS;
 246     return true;
 247 }
 248
 249
 250 template<class TagStore, class Buffering, class Coherence>
 251 Packet *
 252 Cache<TagStore,Buffering,Coherence>::getPacket()
 253 {
 254     assert(missQueue->havePending());
 255     Packet * pkt = missQueue->getPacket();
 256     if (pkt) {
 257         if (!pkt->req->isUncacheable()) {
 258             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 259             BlkType *blk = tags->findBlock(pkt);
 260             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 261                                               (blk)? blk->status : 0);
 262             missQueue->setBusCmd(pkt, cmd);
 263         }
 264     }
 265
 266     assert(!doMasterRequest() || missQueue->havePending());
 267     assert(!pkt || pkt->time <= curTick);
 268     return pkt;
 269 }
 270
 271 template<class TagStore, class Buffering, class Coherence>
 272 void
 273 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
 274 {
 275     if (success && !(pkt->flags & NACKED_LINE)) {
 276         missQueue->markInService(mshr->pkt, mshr);
 277         //Temp Hack for UPGRADES
 278         if (mshr->pkt->cmd == Packet::UpgradeReq) {
 279             pkt->flags &= ~CACHE_LINE_FILL;
 280             BlkType *blk = tags->findBlock(pkt);
 281             CacheBlk::State old_state = (blk) ? blk->status : 0;
 282             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 283             if (old_state != new_state)
 284                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 285                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 286             //Set the state on the upgrade
 287             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 288             PacketList writebacks;
 289             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 290             assert(writebacks.empty());
 291             missQueue->handleResponse(pkt, curTick + hitLatency);
 292         }
 293     } else if (pkt && !pkt->req->isUncacheable()) {
 294         pkt->flags &= ~NACKED_LINE;
 295         pkt->flags &= ~SATISFIED;
 296         pkt->flags &= ~SNOOP_COMMIT;
 297         missQueue->restoreOrigCmd(pkt);
 298     }
 299 }
 300
 301 template<class TagStore, class Buffering, class Coherence>
 302 void
 303 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 304 {
 305     BlkType *blk = NULL;
 306     if (pkt->senderState) {
 307         //Delete temp copy in MSHR, restore it.
 308         delete ((MSHR*)pkt->senderState)->pkt;
 309         ((MSHR*)pkt->senderState)->pkt = pkt;
 310         if (pkt->result == Packet::Nacked) {
 311             //pkt->reinitFromRequest();
 312             warn("NACKs from devices not connected to the same bus not implemented\n");
 313             return;
 314         }
 315         if (pkt->result == Packet::BadAddress) {
 316             //Make the response a Bad address and send it
 317         }
 318 //      MemDebug::cacheResponse(pkt);
 319         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 320                 pkt->getAddr() & (((ULL(1))<<48)-1));
 321
 322         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 323             blk = tags->findBlock(pkt);
 324             CacheBlk::State old_state = (blk) ? blk->status : 0;
 325             PacketList writebacks;
 326             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 327             if (old_state != new_state)
 328                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 329                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 330             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 331                                    new_state, writebacks, pkt);
 332             while (!writebacks.empty()) {
 333                     missQueue->doWriteback(writebacks.front());
 334                     writebacks.pop_front();
 335             }
 336         }
 337         missQueue->handleResponse(pkt, curTick + hitLatency);
 338     }
 339 }
 340
 341 template<class TagStore, class Buffering, class Coherence>
 342 void
 343 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
 344 {
 345     // Need to temporarily move this blk into MSHRs
 346     MSHR *mshr = missQueue->allocateTargetList(addr);
 347     int lat;
 348     PacketList dummy;
 349     // Read the data into the mshr
 350     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 351     assert(dummy.empty());
 352     assert(mshr->pkt->flags & SATISFIED);
 353     // can overload order since it isn't used on non pending blocks
 354     mshr->order = blk->status;
 355     // temporarily remove the block from the cache.
 356     tags->invalidateBlk(addr);
 357 }
 358
 359 template<class TagStore, class Buffering, class Coherence>
 360 void
 361 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 362 {
 363     // Need to temporarily move this blk into MSHRs
 364     assert(mshr->pkt->cmd == Packet::ReadReq);
 365     int lat;
 366     PacketList dummy;
 367     // Read the data into the mshr
 368     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 369     assert(dummy.empty());
 370     assert(mshr->pkt->flags & SATISFIED);
 371     // can overload order since it isn't used on non pending blocks
 372     mshr->order = blk->status;
 373     // temporarily remove the block from the cache.
 374     tags->invalidateBlk(mshr->pkt->getAddr());
 375 }
 376
 377
 378 template<class TagStore, class Buffering, class Coherence>
 379 Packet *
 380 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 381 {
 382     return coherence->getPacket();
 383 }
 384
 385 template<class TagStore, class Buffering, class Coherence>
 386 void
 387 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
 388                                                          MSHR *cshr,
 389                                                          bool success)
 390 {
 391     coherence->sendResult(pkt, cshr, success);
 392 }
 393
 394
 395 template<class TagStore, class Buffering, class Coherence>
 396 void
 397 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 398 {
 399     if (pkt->req->isUncacheable()) {
 400         //Can't get a hit on an uncacheable address
 401         //Revisit this for multi level coherence
 402         return;
 403     }
 404     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 405     BlkType *blk = tags->findBlock(pkt);
 406     MSHR *mshr = missQueue->findMSHR(blk_addr);
 407     if (coherence->hasProtocol()) { //@todo Move this into handle bus req
 408         //If we find an mshr, and it is in service, we need to NACK or invalidate
 409         if (mshr) {
 410             if (mshr->inService) {
 411                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 412                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 413                     //If the outstanding request was an invalidate (upgrade,readex,..)
 414                     //Then we need to ACK the request until we get the data
 415                     //Also NACK if the outstanding request is not a cachefill (writeback)
 416                     assert(!(pkt->flags & SATISFIED));
 417                     pkt->flags |= SATISFIED;
 418                     pkt->flags |= NACKED_LINE;
 419                     ///@todo NACK's from other levels
 420                     //warn("NACKs from devices not connected to the same bus not implemented\n");
 421                     //respondToSnoop(pkt, curTick + hitLatency);
 422                     return;
 423                 }
 424                 else {
 425                     //The supplier will be someone else, because we are waiting for
 426                     //the data.  This should cause this cache to be forced to go to
 427                     //the shared state, not the exclusive even though the shared line
 428                     //won't be asserted.  But for now we will just invlidate ourselves
 429                     //and allow the other cache to go into the exclusive state.
 430                     //@todo Make it so a read to a pending read doesn't invalidate.
 431                     //@todo Make it so that a read to a pending read can't be exclusive now.
 432
 433                     //Set the address so find match works
 434                     //panic("Don't have invalidates yet\n");
 435                     invalidatePkt->addrOverride(pkt->getAddr());
 436
 437                     //Append the invalidate on
 438                     missQueue->addTarget(mshr,invalidatePkt);
 439                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 440                     return;
 441                 }
 442             }
 443         }
 444         //We also need to check the writeback buffers and handle those
 445         std::vector<MSHR *> writebacks;
 446         if (missQueue->findWrites(blk_addr, writebacks)) {
 447             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 448
 449             //Look through writebacks for any non-uncachable writes, use that
 450             for (int i=0; i<writebacks.size(); i++) {
 451                 mshr = writebacks[i];
 452
 453                 if (!mshr->pkt->req->isUncacheable()) {
 454                     if (pkt->isRead()) {
 455                         //Only Upgrades don't get here
 456                         //Supply the data
 457                         assert(!(pkt->flags & SATISFIED));
 458                         pkt->flags |= SATISFIED;
 459
 460                         //If we are in an exclusive protocol, make it ask again
 461                         //to get write permissions (upgrade), signal shared
 462                         pkt->flags |= SHARED_LINE;
 463
 464                         assert(pkt->isRead());
 465                         Addr offset = pkt->getAddr() & (blkSize - 1);
 466                         assert(offset < blkSize);
 467                         assert(pkt->getSize() <= blkSize);
 468                         assert(offset + pkt->getSize() <=blkSize);
 469                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 470
 471                         respondToSnoop(pkt, curTick + hitLatency);
 472                     }
 473
 474                     if (pkt->isInvalidate()) {
 475                         //This must be an upgrade or other cache will take ownership
 476                         missQueue->markInService(mshr->pkt, mshr);
 477                     }
 478                     return;
 479                 }
 480             }
 481         }
 482     }
 483     CacheBlk::State new_state;
 484     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 485     if (satisfy) {
 486         DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 487                 "new state is %i\n",
 488                 pkt->cmdString(), blk_addr, new_state);
 489
 490         tags->handleSnoop(blk, new_state, pkt);
 491         respondToSnoop(pkt, curTick + hitLatency);
 492         return;
 493     }
 494     if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 495                      pkt->cmdString(), blk_addr, new_state);
 496     tags->handleSnoop(blk, new_state);
 497 }
 498
 499 template<class TagStore, class Buffering, class Coherence>
 500 void
 501 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 502 {
 503     //Need to handle the response, if NACKED
 504     if (pkt->flags & NACKED_LINE) {
 505         //Need to mark it as not in service, and retry for bus
 506         assert(0); //Yeah, we saw a NACK come through
 507
 508         //For now this should never get called, we return false when we see a NACK
 509         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 510         //For now it retrys in just 2 cycles, need to figure out how to change that
 511         //Eventually we will want to also have success come in as a parameter
 512         //Need to make sure that we handle the functionality that happens on successufl
 513         //return of the sendAddr function
 514     }
 515 }
 516
 517 template<class TagStore, class Buffering, class Coherence>
 518 void
 519 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 520 {
 521     tags->invalidateBlk(addr);
 522 }
 523
 524
 525 /**
 526  * @todo Fix to not assume write allocate
 527  */
 528 template<class TagStore, class Buffering, class Coherence>
 529 Tick
 530 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
 531 {
 532 //    MemDebug::cacheProbe(pkt);
 533     if (!pkt->req->isUncacheable()) {
 534         if (pkt->isInvalidate() && !pkt->isRead()
 535             && !pkt->isWrite()) {
 536             //Upgrade or Invalidate, satisfy it, don't forward
 537             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 538                     pkt->getAddr() & (((ULL(1))<<48)-1),
 539                     pkt->getAddr() & ~((Addr)blkSize - 1));
 540             pkt->flags |= SATISFIED;
 541             return 0;
 542         }
 543     }
 544
 545     PacketList writebacks;
 546     int lat;
 547     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 548
 549     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 550             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 551             pkt->getAddr() & ~((Addr)blkSize - 1));
 552
 553     if (!blk) {
 554         // Need to check for outstanding misses and writes
 555         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 556
 557         // There can only be one matching outstanding miss.
 558         MSHR* mshr = missQueue->findMSHR(blk_addr);
 559
 560         // There can be many matching outstanding writes.
 561         std::vector<MSHR*> writes;
 562         missQueue->findWrites(blk_addr, writes);
 563
 564         if (!update) {
 565                 otherSidePort->sendFunctional(pkt);
 566
 567             // Check for data in MSHR and writebuffer.
 568             if (mshr) {
 569                 warn("Found outstanding miss on an non-update probe");
 570                 MSHR::TargetList *targets = mshr->getTargetList();
 571                 MSHR::TargetList::iterator i = targets->begin();
 572                 MSHR::TargetList::iterator end = targets->end();
 573                 for (; i != end; ++i) {
 574                     Packet * target = *i;
 575                     // If the target contains data, and it overlaps the
 576                     // probed request, need to update data
 577                     if (target->isWrite() && target->intersect(pkt)) {
 578                         uint8_t* pkt_data;
 579                         uint8_t* write_data;
 580                         int data_size;
 581                         if (target->getAddr() < pkt->getAddr()) {
 582                             int offset = pkt->getAddr() - target->getAddr();
 583                             pkt_data = pkt->getPtr<uint8_t>();
 584                             write_data = target->getPtr<uint8_t>() + offset;
 585                             data_size = target->getSize() - offset;
 586                             assert(data_size > 0);
 587                             if (data_size > pkt->getSize())
 588                                 data_size = pkt->getSize();
 589                         } else {
 590                             int offset = target->getAddr() - pkt->getAddr();
 591                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 592                             write_data = target->getPtr<uint8_t>();
 593                             data_size = pkt->getSize() - offset;
 594                             assert(data_size > pkt->getSize());
 595                             if (data_size > target->getSize())
 596                                 data_size = target->getSize();
 597                         }
 598
 599                         if (pkt->isWrite()) {
 600                             memcpy(pkt_data, write_data, data_size);
 601                         } else {
 602                             memcpy(write_data, pkt_data, data_size);
 603                         }
 604                     }
 605                 }
 606             }
 607             for (int i = 0; i < writes.size(); ++i) {
 608                 Packet * write = writes[i]->pkt;
 609                 if (write->intersect(pkt)) {
 610                     warn("Found outstanding write on an non-update probe");
 611                     uint8_t* pkt_data;
 612                     uint8_t* write_data;
 613                     int data_size;
 614                     if (write->getAddr() < pkt->getAddr()) {
 615                         int offset = pkt->getAddr() - write->getAddr();
 616                         pkt_data = pkt->getPtr<uint8_t>();
 617                         write_data = write->getPtr<uint8_t>() + offset;
 618                         data_size = write->getSize() - offset;
 619                         assert(data_size > 0);
 620                         if (data_size > pkt->getSize())
 621                             data_size = pkt->getSize();
 622                     } else {
 623                         int offset = write->getAddr() - pkt->getAddr();
 624                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 625                         write_data = write->getPtr<uint8_t>();
 626                         data_size = pkt->getSize() - offset;
 627                         assert(data_size > pkt->getSize());
 628                         if (data_size > write->getSize())
 629                             data_size = write->getSize();
 630                     }
 631
 632                     if (pkt->isWrite()) {
 633                         memcpy(pkt_data, write_data, data_size);
 634                     } else {
 635                         memcpy(write_data, pkt_data, data_size);
 636                     }
 637
 638                 }
 639             }
 640             return 0;
 641         } else {
 642             // update the cache state and statistics
 643             if (mshr || !writes.empty()){
 644                 // Can't handle it, return pktuest unsatisfied.
 645                 panic("Atomic access ran into outstanding MSHR's or WB's!");
 646             }
 647             if (!pkt->req->isUncacheable()) {
 648                 // Fetch the cache block to fill
 649                 BlkType *blk = tags->findBlock(pkt);
 650                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 651                                                    (blk)? blk->status : 0);
 652
 653                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 654
 655                 busPkt->allocate();
 656
 657                 busPkt->time = curTick;
 658
 659                 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
 660                         busPkt->cmdString(),
 661                         busPkt->getAddr() & (((ULL(1))<<48)-1),
 662                         busPkt->getAddr() & ~((Addr)blkSize - 1));
 663
 664                 lat = memSidePort->sendAtomic(busPkt);
 665
 666                 //Be sure to flip the response to a request for coherence
 667                 if (busPkt->needsResponse()) {
 668                     busPkt->makeAtomicResponse();
 669                 }
 670
 671 /*              if (!(busPkt->flags & SATISFIED)) {
 672                     // blocked at a higher level, just return
 673                     return 0;
 674                 }
 675
 676 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 677
 678                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 679                 CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
 680                     DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
 681                             busPkt->cmdString(),
 682                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
 683                 if (old_state != new_state)
 684                     DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 685                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 686
 687                 tags->handleFill(blk, busPkt,
 688                                  new_state,
 689                                  writebacks, pkt);
 690                 //Free the packet
 691                 delete busPkt;
 692
 693                 // Handle writebacks if needed
 694                 while (!writebacks.empty()){
 695                     Packet *wbPkt = writebacks.front();
 696                     memSidePort->sendAtomic(wbPkt);
 697                     writebacks.pop_front();
 698                     delete wbPkt;
 699                 }
 700                 return lat + hitLatency;
 701             } else {
 702                 return memSidePort->sendAtomic(pkt);
 703             }
 704         }
 705     } else {
 706         // There was a cache hit.
 707         // Handle writebacks if needed
 708         while (!writebacks.empty()){
 709             memSidePort->sendAtomic(writebacks.front());
 710             writebacks.pop_front();
 711         }
 712
 713         if (update) {
 714             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 715         } else if (pkt->isWrite()) {
 716             // Still need to change data in all locations.
 717             otherSidePort->sendFunctional(pkt);
 718         }
 719         return hitLatency;
 720     }
 721     fatal("Probe not handled.\n");
 722     return 0;
 723 }
 724
 725 template<class TagStore, class Buffering, class Coherence>
 726 Tick
 727 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 728 {
 729         Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 730         BlkType *blk = tags->findBlock(pkt);
 731         MSHR *mshr = missQueue->findMSHR(blk_addr);
 732         CacheBlk::State new_state = 0;
 733         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 734         if (satisfy) {
 735             DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 736                     "new state is %i\n",
 737                     pkt->cmdString(), blk_addr, new_state);
 738
 739             tags->handleSnoop(blk, new_state, pkt);
 740             return hitLatency;
 741         }
 742         if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 743                      pkt->cmdString(), blk_addr, new_state);
 744         tags->handleSnoop(blk, new_state);
 745         return 0;
 746 }
 747