src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(Packet *pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         //Temporary solution to LL/SC
  90         if (pkt->isWrite() && (pkt->req->isLocked())) {
  91             pkt->req->setScResult(1);
  92         }
  93
  94         probe(pkt, true, NULL);
  95         //TEMP ALWAYS SUCCES FOR NOW
  96         pkt->result = Packet::Success;
  97     }
  98     else
  99     {
 100         if (pkt->isResponse())
 101             handleResponse(pkt);
 102         else
 103             return snoopProbe(pkt);
 104     }
 105     //Fix this timing info
 106     return hitLatency;
 107 }
 108
 109 template<class TagStore, class Buffering, class Coherence>
 110 void
 111 Cache<TagStore,Buffering,Coherence>::
 112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 113 {
 114     if (isCpuSide)
 115     {
 116         //TEMP USE CPU?THREAD 0 0
 117         pkt->req->setThreadContext(0,0);
 118
 119         //Temporary solution to LL/SC
 120         if (pkt->isWrite() && (pkt->req->isLocked())) {
 121             assert("Can't handle LL/SC on functional path\n");
 122         }
 123
 124         probe(pkt, false, memSidePort);
 125         //TEMP ALWAYS SUCCESFUL FOR NOW
 126         pkt->result = Packet::Success;
 127     }
 128     else
 129     {
 130             probe(pkt, false, cpuSidePort);
 131     }
 132 }
 133
 134 template<class TagStore, class Buffering, class Coherence>
 135 void
 136 Cache<TagStore,Buffering,Coherence>::
 137 recvStatusChange(Port::Status status, bool isCpuSide)
 138 {
 139
 140 }
 141
 142
 143 template<class TagStore, class Buffering, class Coherence>
 144 Cache<TagStore,Buffering,Coherence>::
 145 Cache(const std::string &_name,
 146       Cache<TagStore,Buffering,Coherence>::Params &params)
 147     : BaseCache(_name, params.baseParams),
 148       prefetchAccess(params.prefetchAccess),
 149       tags(params.tags), missQueue(params.missQueue),
 150       coherence(params.coherence), prefetcher(params.prefetcher),
 151       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
 152       hitLatency(params.hitLatency)
 153 {
 154 //FIX BUS POINTERS
 155 //    if (params.in == NULL) {
 156         topLevelCache = true;
 157 //    }
 158 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
 159         tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
 160     tags->setPrefetcher(prefetcher);
 161     missQueue->setCache(this);
 162     missQueue->setPrefetcher(prefetcher);
 163     coherence->setCache(this);
 164     prefetcher->setCache(this);
 165     prefetcher->setTags(tags);
 166     prefetcher->setBuffer(missQueue);
 167     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 168     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 169 }
 170
 171 template<class TagStore, class Buffering, class Coherence>
 172 void
 173 Cache<TagStore,Buffering,Coherence>::regStats()
 174 {
 175     BaseCache::regStats();
 176     tags->regStats(name());
 177     missQueue->regStats(name());
 178     coherence->regStats(name());
 179     prefetcher->regStats(name());
 180 }
 181
 182 template<class TagStore, class Buffering, class Coherence>
 183 bool
 184 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 185 {
 186 //@todo Add back in MemDebug Calls
 187 //    MemDebug::cacheAccess(pkt);
 188     BlkType *blk = NULL;
 189     PacketList writebacks;
 190     int size = blkSize;
 191     int lat = hitLatency;
 192     if (prefetchAccess) {
 193         //We are determining prefetches on access stream, call prefetcher
 194         prefetcher->handleMiss(pkt, curTick);
 195     }
 196     if (!pkt->req->isUncacheable()) {
 197         blk = tags->handleAccess(pkt, lat, writebacks);
 198     } else {
 199         size = pkt->getSize();
 200     }
 201     // If this is a block size write/hint (WH64) allocate the block here
 202     // if the coherence protocol allows it.
 203     /** @todo make the fast write alloc (wh64) work with coherence. */
 204     /** @todo Do we want to do fast writes for writebacks as well? */
 205     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 206         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 207         // not outstanding misses, can do this
 208         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 209         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 210             if (outstanding_miss) {
 211                 warn("WriteInv doing a fastallocate"
 212                      "with an outstanding miss to the same address\n");
 213             }
 214             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 215                                    writebacks);
 216             ++fastWrites;
 217         }
 218     }
 219     while (!writebacks.empty()) {
 220         missQueue->doWriteback(writebacks.front());
 221         writebacks.pop_front();
 222     }
 223     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 224             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 225             pkt->getAddr() & ~((Addr)blkSize - 1));
 226     if (blk) {
 227         // Hit
 228         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 229         // clear dirty bit if write through
 230         if (pkt->needsResponse())
 231             respond(pkt, curTick+lat);
 232         if (pkt->cmd == Packet::Writeback) {
 233             //Signal that you can kill the pkt/req
 234             pkt->flags |= SATISFIED;
 235         }
 236         return true;
 237     }
 238
 239     // Miss
 240     if (!pkt->req->isUncacheable()) {
 241         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 242         /** @todo Move miss count code into BaseCache */
 243         if (missCount) {
 244             --missCount;
 245             if (missCount == 0)
 246                 exitSimLoop("A cache reached the maximum miss count");
 247         }
 248     }
 249     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 250 //    return MA_CACHE_MISS;
 251     return true;
 252 }
 253
 254
 255 template<class TagStore, class Buffering, class Coherence>
 256 Packet *
 257 Cache<TagStore,Buffering,Coherence>::getPacket()
 258 {
 259     assert(missQueue->havePending());
 260     Packet * pkt = missQueue->getPacket();
 261     if (pkt) {
 262         if (!pkt->req->isUncacheable()) {
 263             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 264             BlkType *blk = tags->findBlock(pkt);
 265             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 266                                               (blk)? blk->status : 0);
 267             missQueue->setBusCmd(pkt, cmd);
 268         }
 269     }
 270
 271     assert(!doMasterRequest() || missQueue->havePending());
 272     assert(!pkt || pkt->time <= curTick);
 273     return pkt;
 274 }
 275
 276 template<class TagStore, class Buffering, class Coherence>
 277 void
 278 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
 279 {
 280     if (success && !(pkt->flags & NACKED_LINE)) {
 281         missQueue->markInService(pkt, mshr);
 282         //Temp Hack for UPGRADES
 283         if (pkt->cmd == Packet::UpgradeReq) {
 284             pkt->flags &= ~CACHE_LINE_FILL;
 285             BlkType *blk = tags->findBlock(pkt);
 286             CacheBlk::State old_state = (blk) ? blk->status : 0;
 287             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 288             if (old_state != new_state)
 289                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 290                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 291             //Set the state on the upgrade
 292             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 293             PacketList writebacks;
 294             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 295             assert(writebacks.empty());
 296             missQueue->handleResponse(pkt, curTick + hitLatency);
 297         }
 298     } else if (pkt && !pkt->req->isUncacheable()) {
 299         pkt->flags &= ~NACKED_LINE;
 300         pkt->flags &= ~SATISFIED;
 301         pkt->flags &= ~SNOOP_COMMIT;
 302         missQueue->restoreOrigCmd(pkt);
 303     }
 304 }
 305
 306 template<class TagStore, class Buffering, class Coherence>
 307 void
 308 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 309 {
 310     BlkType *blk = NULL;
 311     if (pkt->senderState) {
 312         if (pkt->result == Packet::Nacked) {
 313             //pkt->reinitFromRequest();
 314             warn("NACKs from devices not connected to the same bus not implemented\n");
 315             return;
 316         }
 317         if (pkt->result == Packet::BadAddress) {
 318             //Make the response a Bad address and send it
 319         }
 320 //      MemDebug::cacheResponse(pkt);
 321         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 322                 pkt->getAddr() & (((ULL(1))<<48)-1));
 323
 324         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 325             blk = tags->findBlock(pkt);
 326             CacheBlk::State old_state = (blk) ? blk->status : 0;
 327             PacketList writebacks;
 328             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 329             if (old_state != new_state)
 330                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 331                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 332             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 333                                    new_state, writebacks, pkt);
 334             while (!writebacks.empty()) {
 335                     missQueue->doWriteback(writebacks.front());
 336                     writebacks.pop_front();
 337             }
 338         }
 339         missQueue->handleResponse(pkt, curTick + hitLatency);
 340     }
 341 }
 342
 343 template<class TagStore, class Buffering, class Coherence>
 344 void
 345 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
 346 {
 347     // Need to temporarily move this blk into MSHRs
 348     MSHR *mshr = missQueue->allocateTargetList(addr);
 349     int lat;
 350     PacketList dummy;
 351     // Read the data into the mshr
 352     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 353     assert(dummy.empty());
 354     assert(mshr->pkt->flags & SATISFIED);
 355     // can overload order since it isn't used on non pending blocks
 356     mshr->order = blk->status;
 357     // temporarily remove the block from the cache.
 358     tags->invalidateBlk(addr);
 359 }
 360
 361 template<class TagStore, class Buffering, class Coherence>
 362 void
 363 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 364 {
 365     // Need to temporarily move this blk into MSHRs
 366     assert(mshr->pkt->cmd == Packet::ReadReq);
 367     int lat;
 368     PacketList dummy;
 369     // Read the data into the mshr
 370     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 371     assert(dummy.empty());
 372     assert(mshr->pkt->flags & SATISFIED);
 373     // can overload order since it isn't used on non pending blocks
 374     mshr->order = blk->status;
 375     // temporarily remove the block from the cache.
 376     tags->invalidateBlk(mshr->pkt->getAddr());
 377 }
 378
 379
 380 template<class TagStore, class Buffering, class Coherence>
 381 Packet *
 382 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 383 {
 384     return coherence->getPacket();
 385 }
 386
 387
 388 template<class TagStore, class Buffering, class Coherence>
 389 void
 390 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 391 {
 392     if (pkt->req->isUncacheable()) {
 393         //Can't get a hit on an uncacheable address
 394         //Revisit this for multi level coherence
 395         return;
 396     }
 397     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 398     BlkType *blk = tags->findBlock(pkt);
 399     MSHR *mshr = missQueue->findMSHR(blk_addr);
 400     if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
 401         //If we find an mshr, and it is in service, we need to NACK or invalidate
 402         if (mshr) {
 403             if (mshr->inService) {
 404                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 405                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 406                     //If the outstanding request was an invalidate (upgrade,readex,..)
 407                     //Then we need to ACK the request until we get the data
 408                     //Also NACK if the outstanding request is not a cachefill (writeback)
 409                     assert(!(pkt->flags & SATISFIED));
 410                     pkt->flags |= SATISFIED;
 411                     pkt->flags |= NACKED_LINE;
 412                     ///@todo NACK's from other levels
 413                     //warn("NACKs from devices not connected to the same bus not implemented\n");
 414                     //respondToSnoop(pkt, curTick + hitLatency);
 415                     return;
 416                 }
 417                 else {
 418                     //The supplier will be someone else, because we are waiting for
 419                     //the data.  This should cause this cache to be forced to go to
 420                     //the shared state, not the exclusive even though the shared line
 421                     //won't be asserted.  But for now we will just invlidate ourselves
 422                     //and allow the other cache to go into the exclusive state.
 423                     //@todo Make it so a read to a pending read doesn't invalidate.
 424                     //@todo Make it so that a read to a pending read can't be exclusive now.
 425
 426                     //Set the address so find match works
 427                     //panic("Don't have invalidates yet\n");
 428                     invalidatePkt->addrOverride(pkt->getAddr());
 429
 430                     //Append the invalidate on
 431                     missQueue->addTarget(mshr,invalidatePkt);
 432                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 433                     return;
 434                 }
 435             }
 436         }
 437         //We also need to check the writeback buffers and handle those
 438         std::vector<MSHR *> writebacks;
 439         if (missQueue->findWrites(blk_addr, writebacks)) {
 440             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 441
 442             //Look through writebacks for any non-uncachable writes, use that
 443             for (int i=0; i<writebacks.size(); i++) {
 444                 mshr = writebacks[i];
 445
 446                 if (!mshr->pkt->req->isUncacheable()) {
 447                     if (pkt->isRead()) {
 448                         //Only Upgrades don't get here
 449                         //Supply the data
 450                         assert(!(pkt->flags & SATISFIED));
 451                         pkt->flags |= SATISFIED;
 452
 453                         //If we are in an exclusive protocol, make it ask again
 454                         //to get write permissions (upgrade), signal shared
 455                         pkt->flags |= SHARED_LINE;
 456
 457                         assert(pkt->isRead());
 458                         Addr offset = pkt->getAddr() & (blkSize - 1);
 459                         assert(offset < blkSize);
 460                         assert(pkt->getSize() <= blkSize);
 461                         assert(offset + pkt->getSize() <=blkSize);
 462                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 463
 464                         respondToSnoop(pkt, curTick + hitLatency);
 465                     }
 466
 467                     if (pkt->isInvalidate()) {
 468                         //This must be an upgrade or other cache will take ownership
 469                         missQueue->markInService(mshr->pkt, mshr);
 470                     }
 471                     return;
 472                 }
 473             }
 474         }
 475     }
 476     CacheBlk::State new_state;
 477     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 478     if (satisfy) {
 479         DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 480                 "new state is %i\n",
 481                 pkt->cmdString(), blk_addr, new_state);
 482
 483         tags->handleSnoop(blk, new_state, pkt);
 484         respondToSnoop(pkt, curTick + hitLatency);
 485         return;
 486     }
 487     if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 488                      pkt->cmdString(), blk_addr, new_state);
 489     tags->handleSnoop(blk, new_state);
 490 }
 491
 492 template<class TagStore, class Buffering, class Coherence>
 493 void
 494 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 495 {
 496     //Need to handle the response, if NACKED
 497     if (pkt->flags & NACKED_LINE) {
 498         //Need to mark it as not in service, and retry for bus
 499         assert(0); //Yeah, we saw a NACK come through
 500
 501         //For now this should never get called, we return false when we see a NACK
 502         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 503         //For now it retrys in just 2 cycles, need to figure out how to change that
 504         //Eventually we will want to also have success come in as a parameter
 505         //Need to make sure that we handle the functionality that happens on successufl
 506         //return of the sendAddr function
 507     }
 508 }
 509
 510 template<class TagStore, class Buffering, class Coherence>
 511 void
 512 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 513 {
 514     tags->invalidateBlk(addr);
 515 }
 516
 517
 518 /**
 519  * @todo Fix to not assume write allocate
 520  */
 521 template<class TagStore, class Buffering, class Coherence>
 522 Tick
 523 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
 524 {
 525 //    MemDebug::cacheProbe(pkt);
 526     if (!pkt->req->isUncacheable()) {
 527         if (pkt->isInvalidate() && !pkt->isRead()
 528             && !pkt->isWrite()) {
 529             //Upgrade or Invalidate, satisfy it, don't forward
 530             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 531                     pkt->getAddr() & (((ULL(1))<<48)-1),
 532                     pkt->getAddr() & ~((Addr)blkSize - 1));
 533             pkt->flags |= SATISFIED;
 534             return 0;
 535         }
 536     }
 537
 538     PacketList writebacks;
 539     int lat;
 540     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 541
 542     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 543             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 544             pkt->getAddr() & ~((Addr)blkSize - 1));
 545
 546     if (!blk) {
 547         // Need to check for outstanding misses and writes
 548         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 549
 550         // There can only be one matching outstanding miss.
 551         MSHR* mshr = missQueue->findMSHR(blk_addr);
 552
 553         // There can be many matching outstanding writes.
 554         std::vector<MSHR*> writes;
 555         missQueue->findWrites(blk_addr, writes);
 556
 557         if (!update) {
 558                 otherSidePort->sendFunctional(pkt);
 559
 560             // Check for data in MSHR and writebuffer.
 561             if (mshr) {
 562                 warn("Found outstanding miss on an non-update probe");
 563                 MSHR::TargetList *targets = mshr->getTargetList();
 564                 MSHR::TargetList::iterator i = targets->begin();
 565                 MSHR::TargetList::iterator end = targets->end();
 566                 for (; i != end; ++i) {
 567                     Packet * target = *i;
 568                     // If the target contains data, and it overlaps the
 569                     // probed request, need to update data
 570                     if (target->isWrite() && target->intersect(pkt)) {
 571                         uint8_t* pkt_data;
 572                         uint8_t* write_data;
 573                         int data_size;
 574                         if (target->getAddr() < pkt->getAddr()) {
 575                             int offset = pkt->getAddr() - target->getAddr();
 576                             pkt_data = pkt->getPtr<uint8_t>();
 577                             write_data = target->getPtr<uint8_t>() + offset;
 578                             data_size = target->getSize() - offset;
 579                             assert(data_size > 0);
 580                             if (data_size > pkt->getSize())
 581                                 data_size = pkt->getSize();
 582                         } else {
 583                             int offset = target->getAddr() - pkt->getAddr();
 584                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 585                             write_data = target->getPtr<uint8_t>();
 586                             data_size = pkt->getSize() - offset;
 587                             assert(data_size > pkt->getSize());
 588                             if (data_size > target->getSize())
 589                                 data_size = target->getSize();
 590                         }
 591
 592                         if (pkt->isWrite()) {
 593                             memcpy(pkt_data, write_data, data_size);
 594                         } else {
 595                             memcpy(write_data, pkt_data, data_size);
 596                         }
 597                     }
 598                 }
 599             }
 600             for (int i = 0; i < writes.size(); ++i) {
 601                 Packet * write = writes[i]->pkt;
 602                 if (write->intersect(pkt)) {
 603                     warn("Found outstanding write on an non-update probe");
 604                     uint8_t* pkt_data;
 605                     uint8_t* write_data;
 606                     int data_size;
 607                     if (write->getAddr() < pkt->getAddr()) {
 608                         int offset = pkt->getAddr() - write->getAddr();
 609                         pkt_data = pkt->getPtr<uint8_t>();
 610                         write_data = write->getPtr<uint8_t>() + offset;
 611                         data_size = write->getSize() - offset;
 612                         assert(data_size > 0);
 613                         if (data_size > pkt->getSize())
 614                             data_size = pkt->getSize();
 615                     } else {
 616                         int offset = write->getAddr() - pkt->getAddr();
 617                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 618                         write_data = write->getPtr<uint8_t>();
 619                         data_size = pkt->getSize() - offset;
 620                         assert(data_size > pkt->getSize());
 621                         if (data_size > write->getSize())
 622                             data_size = write->getSize();
 623                     }
 624
 625                     if (pkt->isWrite()) {
 626                         memcpy(pkt_data, write_data, data_size);
 627                     } else {
 628                         memcpy(write_data, pkt_data, data_size);
 629                     }
 630
 631                 }
 632             }
 633             return 0;
 634         } else {
 635             // update the cache state and statistics
 636             if (mshr || !writes.empty()){
 637                 // Can't handle it, return pktuest unsatisfied.
 638                 panic("Atomic access ran into outstanding MSHR's or WB's!");
 639             }
 640             if (!pkt->req->isUncacheable()) {
 641                 // Fetch the cache block to fill
 642                 BlkType *blk = tags->findBlock(pkt);
 643                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 644                                                    (blk)? blk->status : 0);
 645
 646                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 647
 648                 busPkt->allocate();
 649
 650                 busPkt->time = curTick;
 651
 652                 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
 653                         busPkt->cmdString(),
 654                         busPkt->getAddr() & (((ULL(1))<<48)-1),
 655                         busPkt->getAddr() & ~((Addr)blkSize - 1));
 656
 657                 lat = memSidePort->sendAtomic(busPkt);
 658
 659                 //Be sure to flip the response to a request for coherence
 660                 if (busPkt->needsResponse()) {
 661                     busPkt->makeAtomicResponse();
 662                 }
 663
 664 /*              if (!(busPkt->flags & SATISFIED)) {
 665                     // blocked at a higher level, just return
 666                     return 0;
 667                 }
 668
 669 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 670
 671                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 672                 CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
 673                     DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
 674                             busPkt->cmdString(),
 675                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
 676                 if (old_state != new_state)
 677                     DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 678                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 679
 680                 tags->handleFill(blk, busPkt,
 681                                  new_state,
 682                                  writebacks, pkt);
 683                 //Free the packet
 684                 delete busPkt;
 685
 686                 // Handle writebacks if needed
 687                 while (!writebacks.empty()){
 688                     Packet *wbPkt = writebacks.front();
 689                     memSidePort->sendAtomic(wbPkt);
 690                     writebacks.pop_front();
 691                     delete wbPkt;
 692                 }
 693                 return lat + hitLatency;
 694             } else {
 695                 return memSidePort->sendAtomic(pkt);
 696             }
 697         }
 698     } else {
 699         // There was a cache hit.
 700         // Handle writebacks if needed
 701         while (!writebacks.empty()){
 702             memSidePort->sendAtomic(writebacks.front());
 703             writebacks.pop_front();
 704         }
 705
 706         if (update) {
 707             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 708         } else if (pkt->isWrite()) {
 709             // Still need to change data in all locations.
 710             otherSidePort->sendFunctional(pkt);
 711         }
 712         return hitLatency;
 713     }
 714     fatal("Probe not handled.\n");
 715     return 0;
 716 }
 717
 718 template<class TagStore, class Buffering, class Coherence>
 719 Tick
 720 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 721 {
 722         Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 723         BlkType *blk = tags->findBlock(pkt);
 724         MSHR *mshr = missQueue->findMSHR(blk_addr);
 725         CacheBlk::State new_state = 0;
 726         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 727         if (satisfy) {
 728             DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 729                     "new state is %i\n",
 730                     pkt->cmdString(), blk_addr, new_state);
 731
 732             tags->handleSnoop(blk, new_state, pkt);
 733             return hitLatency;
 734         }
 735         if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 736                      pkt->cmdString(), blk_addr, new_state);
 737         tags->handleSnoop(blk, new_state);
 738         return 0;
 739 }
 740