src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(Packet *pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         //Temporary solution to LL/SC
  90         if (pkt->isWrite() && (pkt->req->isLocked())) {
  91             pkt->req->setScResult(1);
  92         }
  93
  94         probe(pkt, true, NULL);
  95         //TEMP ALWAYS SUCCES FOR NOW
  96         pkt->result = Packet::Success;
  97     }
  98     else
  99     {
 100         if (pkt->isResponse())
 101             handleResponse(pkt);
 102         else
 103             return snoopProbe(pkt);
 104     }
 105     //Fix this timing info
 106     return hitLatency;
 107 }
 108
 109 template<class TagStore, class Buffering, class Coherence>
 110 void
 111 Cache<TagStore,Buffering,Coherence>::
 112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 113 {
 114     if (isCpuSide)
 115     {
 116         //TEMP USE CPU?THREAD 0 0
 117         pkt->req->setThreadContext(0,0);
 118
 119         //Temporary solution to LL/SC
 120         if (pkt->isWrite() && (pkt->req->isLocked())) {
 121             assert("Can't handle LL/SC on functional path\n");
 122         }
 123
 124         probe(pkt, false, memSidePort);
 125         //TEMP ALWAYS SUCCESFUL FOR NOW
 126         pkt->result = Packet::Success;
 127     }
 128     else
 129     {
 130             probe(pkt, false, cpuSidePort);
 131     }
 132 }
 133
 134 template<class TagStore, class Buffering, class Coherence>
 135 void
 136 Cache<TagStore,Buffering,Coherence>::
 137 recvStatusChange(Port::Status status, bool isCpuSide)
 138 {
 139
 140 }
 141
 142
 143 template<class TagStore, class Buffering, class Coherence>
 144 Cache<TagStore,Buffering,Coherence>::
 145 Cache(const std::string &_name,
 146       Cache<TagStore,Buffering,Coherence>::Params &params)
 147     : BaseCache(_name, params.baseParams),
 148       prefetchAccess(params.prefetchAccess),
 149       tags(params.tags), missQueue(params.missQueue),
 150       coherence(params.coherence), prefetcher(params.prefetcher),
 151       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
 152       hitLatency(params.hitLatency)
 153 {
 154     tags->setCache(this);
 155     tags->setPrefetcher(prefetcher);
 156     missQueue->setCache(this);
 157     missQueue->setPrefetcher(prefetcher);
 158     coherence->setCache(this);
 159     prefetcher->setCache(this);
 160     prefetcher->setTags(tags);
 161     prefetcher->setBuffer(missQueue);
 162     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 163     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 164 }
 165
 166 template<class TagStore, class Buffering, class Coherence>
 167 void
 168 Cache<TagStore,Buffering,Coherence>::regStats()
 169 {
 170     BaseCache::regStats();
 171     tags->regStats(name());
 172     missQueue->regStats(name());
 173     coherence->regStats(name());
 174     prefetcher->regStats(name());
 175 }
 176
 177 template<class TagStore, class Buffering, class Coherence>
 178 bool
 179 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 180 {
 181 //@todo Add back in MemDebug Calls
 182 //    MemDebug::cacheAccess(pkt);
 183     BlkType *blk = NULL;
 184     PacketList writebacks;
 185     int size = blkSize;
 186     int lat = hitLatency;
 187     if (prefetchAccess) {
 188         //We are determining prefetches on access stream, call prefetcher
 189         prefetcher->handleMiss(pkt, curTick);
 190     }
 191     if (!pkt->req->isUncacheable()) {
 192         blk = tags->handleAccess(pkt, lat, writebacks);
 193     } else {
 194         size = pkt->getSize();
 195     }
 196     // If this is a block size write/hint (WH64) allocate the block here
 197     // if the coherence protocol allows it.
 198     /** @todo make the fast write alloc (wh64) work with coherence. */
 199     /** @todo Do we want to do fast writes for writebacks as well? */
 200     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 201         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 202         // not outstanding misses, can do this
 203         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 204         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 205             if (outstanding_miss) {
 206                 warn("WriteInv doing a fastallocate"
 207                      "with an outstanding miss to the same address\n");
 208             }
 209             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 210                                    writebacks);
 211             ++fastWrites;
 212         }
 213     }
 214     while (!writebacks.empty()) {
 215         missQueue->doWriteback(writebacks.front());
 216         writebacks.pop_front();
 217     }
 218     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 219             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 220             pkt->getAddr() & ~((Addr)blkSize - 1));
 221     if (blk) {
 222         // Hit
 223         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 224         // clear dirty bit if write through
 225         if (pkt->needsResponse())
 226             respond(pkt, curTick+lat);
 227         if (pkt->cmd == Packet::Writeback) {
 228             //Signal that you can kill the pkt/req
 229             pkt->flags |= SATISFIED;
 230         }
 231         return true;
 232     }
 233
 234     // Miss
 235     if (!pkt->req->isUncacheable()) {
 236         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 237         /** @todo Move miss count code into BaseCache */
 238         if (missCount) {
 239             --missCount;
 240             if (missCount == 0)
 241                 exitSimLoop("A cache reached the maximum miss count");
 242         }
 243     }
 244     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 245 //    return MA_CACHE_MISS;
 246     return true;
 247 }
 248
 249
 250 template<class TagStore, class Buffering, class Coherence>
 251 Packet *
 252 Cache<TagStore,Buffering,Coherence>::getPacket()
 253 {
 254     assert(missQueue->havePending());
 255     Packet * pkt = missQueue->getPacket();
 256     if (pkt) {
 257         if (!pkt->req->isUncacheable()) {
 258             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 259             BlkType *blk = tags->findBlock(pkt);
 260             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 261                                               (blk)? blk->status : 0);
 262             missQueue->setBusCmd(pkt, cmd);
 263         }
 264     }
 265
 266     assert(!doMasterRequest() || missQueue->havePending());
 267     assert(!pkt || pkt->time <= curTick);
 268     return pkt;
 269 }
 270
 271 template<class TagStore, class Buffering, class Coherence>
 272 void
 273 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
 274 {
 275     if (success && !(pkt->flags & NACKED_LINE)) {
 276         missQueue->markInService(pkt, mshr);
 277         //Temp Hack for UPGRADES
 278         if (pkt->cmd == Packet::UpgradeReq) {
 279             pkt->flags &= ~CACHE_LINE_FILL;
 280             BlkType *blk = tags->findBlock(pkt);
 281             CacheBlk::State old_state = (blk) ? blk->status : 0;
 282             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 283             if (old_state != new_state)
 284                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 285                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 286             //Set the state on the upgrade
 287             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 288             PacketList writebacks;
 289             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 290             assert(writebacks.empty());
 291             missQueue->handleResponse(pkt, curTick + hitLatency);
 292         }
 293     } else if (pkt && !pkt->req->isUncacheable()) {
 294         pkt->flags &= ~NACKED_LINE;
 295         pkt->flags &= ~SATISFIED;
 296         pkt->flags &= ~SNOOP_COMMIT;
 297         missQueue->restoreOrigCmd(pkt);
 298     }
 299 }
 300
 301 template<class TagStore, class Buffering, class Coherence>
 302 void
 303 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 304 {
 305     BlkType *blk = NULL;
 306     if (pkt->senderState) {
 307         if (pkt->result == Packet::Nacked) {
 308             //pkt->reinitFromRequest();
 309             warn("NACKs from devices not connected to the same bus not implemented\n");
 310             return;
 311         }
 312         if (pkt->result == Packet::BadAddress) {
 313             //Make the response a Bad address and send it
 314         }
 315 //      MemDebug::cacheResponse(pkt);
 316         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 317                 pkt->getAddr() & (((ULL(1))<<48)-1));
 318
 319         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 320             blk = tags->findBlock(pkt);
 321             CacheBlk::State old_state = (blk) ? blk->status : 0;
 322             PacketList writebacks;
 323             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 324             if (old_state != new_state)
 325                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 326                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 327             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 328                                    new_state, writebacks, pkt);
 329             while (!writebacks.empty()) {
 330                     missQueue->doWriteback(writebacks.front());
 331                     writebacks.pop_front();
 332             }
 333         }
 334         missQueue->handleResponse(pkt, curTick + hitLatency);
 335     }
 336 }
 337
 338 template<class TagStore, class Buffering, class Coherence>
 339 void
 340 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
 341 {
 342     // Need to temporarily move this blk into MSHRs
 343     MSHR *mshr = missQueue->allocateTargetList(addr);
 344     int lat;
 345     PacketList dummy;
 346     // Read the data into the mshr
 347     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 348     assert(dummy.empty());
 349     assert(mshr->pkt->flags & SATISFIED);
 350     // can overload order since it isn't used on non pending blocks
 351     mshr->order = blk->status;
 352     // temporarily remove the block from the cache.
 353     tags->invalidateBlk(addr);
 354 }
 355
 356 template<class TagStore, class Buffering, class Coherence>
 357 void
 358 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 359 {
 360     // Need to temporarily move this blk into MSHRs
 361     assert(mshr->pkt->cmd == Packet::ReadReq);
 362     int lat;
 363     PacketList dummy;
 364     // Read the data into the mshr
 365     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 366     assert(dummy.empty());
 367     assert(mshr->pkt->flags & SATISFIED);
 368     // can overload order since it isn't used on non pending blocks
 369     mshr->order = blk->status;
 370     // temporarily remove the block from the cache.
 371     tags->invalidateBlk(mshr->pkt->getAddr());
 372 }
 373
 374
 375 template<class TagStore, class Buffering, class Coherence>
 376 Packet *
 377 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 378 {
 379     return coherence->getPacket();
 380 }
 381
 382
 383 template<class TagStore, class Buffering, class Coherence>
 384 void
 385 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 386 {
 387     if (pkt->req->isUncacheable()) {
 388         //Can't get a hit on an uncacheable address
 389         //Revisit this for multi level coherence
 390         return;
 391     }
 392     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 393     BlkType *blk = tags->findBlock(pkt);
 394     MSHR *mshr = missQueue->findMSHR(blk_addr);
 395     if (coherence->hasProtocol()) { //@todo Move this into handle bus req
 396         //If we find an mshr, and it is in service, we need to NACK or invalidate
 397         if (mshr) {
 398             if (mshr->inService) {
 399                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 400                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 401                     //If the outstanding request was an invalidate (upgrade,readex,..)
 402                     //Then we need to ACK the request until we get the data
 403                     //Also NACK if the outstanding request is not a cachefill (writeback)
 404                     assert(!(pkt->flags & SATISFIED));
 405                     pkt->flags |= SATISFIED;
 406                     pkt->flags |= NACKED_LINE;
 407                     ///@todo NACK's from other levels
 408                     //warn("NACKs from devices not connected to the same bus not implemented\n");
 409                     //respondToSnoop(pkt, curTick + hitLatency);
 410                     return;
 411                 }
 412                 else {
 413                     //The supplier will be someone else, because we are waiting for
 414                     //the data.  This should cause this cache to be forced to go to
 415                     //the shared state, not the exclusive even though the shared line
 416                     //won't be asserted.  But for now we will just invlidate ourselves
 417                     //and allow the other cache to go into the exclusive state.
 418                     //@todo Make it so a read to a pending read doesn't invalidate.
 419                     //@todo Make it so that a read to a pending read can't be exclusive now.
 420
 421                     //Set the address so find match works
 422                     //panic("Don't have invalidates yet\n");
 423                     invalidatePkt->addrOverride(pkt->getAddr());
 424
 425                     //Append the invalidate on
 426                     missQueue->addTarget(mshr,invalidatePkt);
 427                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 428                     return;
 429                 }
 430             }
 431         }
 432         //We also need to check the writeback buffers and handle those
 433         std::vector<MSHR *> writebacks;
 434         if (missQueue->findWrites(blk_addr, writebacks)) {
 435             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 436
 437             //Look through writebacks for any non-uncachable writes, use that
 438             for (int i=0; i<writebacks.size(); i++) {
 439                 mshr = writebacks[i];
 440
 441                 if (!mshr->pkt->req->isUncacheable()) {
 442                     if (pkt->isRead()) {
 443                         //Only Upgrades don't get here
 444                         //Supply the data
 445                         assert(!(pkt->flags & SATISFIED));
 446                         pkt->flags |= SATISFIED;
 447
 448                         //If we are in an exclusive protocol, make it ask again
 449                         //to get write permissions (upgrade), signal shared
 450                         pkt->flags |= SHARED_LINE;
 451
 452                         assert(pkt->isRead());
 453                         Addr offset = pkt->getAddr() & (blkSize - 1);
 454                         assert(offset < blkSize);
 455                         assert(pkt->getSize() <= blkSize);
 456                         assert(offset + pkt->getSize() <=blkSize);
 457                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 458
 459                         respondToSnoop(pkt, curTick + hitLatency);
 460                     }
 461
 462                     if (pkt->isInvalidate()) {
 463                         //This must be an upgrade or other cache will take ownership
 464                         missQueue->markInService(mshr->pkt, mshr);
 465                     }
 466                     return;
 467                 }
 468             }
 469         }
 470     }
 471     CacheBlk::State new_state;
 472     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 473     if (satisfy) {
 474         DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 475                 "new state is %i\n",
 476                 pkt->cmdString(), blk_addr, new_state);
 477
 478         tags->handleSnoop(blk, new_state, pkt);
 479         respondToSnoop(pkt, curTick + hitLatency);
 480         return;
 481     }
 482     if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 483                      pkt->cmdString(), blk_addr, new_state);
 484     tags->handleSnoop(blk, new_state);
 485 }
 486
 487 template<class TagStore, class Buffering, class Coherence>
 488 void
 489 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 490 {
 491     //Need to handle the response, if NACKED
 492     if (pkt->flags & NACKED_LINE) {
 493         //Need to mark it as not in service, and retry for bus
 494         assert(0); //Yeah, we saw a NACK come through
 495
 496         //For now this should never get called, we return false when we see a NACK
 497         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 498         //For now it retrys in just 2 cycles, need to figure out how to change that
 499         //Eventually we will want to also have success come in as a parameter
 500         //Need to make sure that we handle the functionality that happens on successufl
 501         //return of the sendAddr function
 502     }
 503 }
 504
 505 template<class TagStore, class Buffering, class Coherence>
 506 void
 507 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 508 {
 509     tags->invalidateBlk(addr);
 510 }
 511
 512
 513 /**
 514  * @todo Fix to not assume write allocate
 515  */
 516 template<class TagStore, class Buffering, class Coherence>
 517 Tick
 518 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
 519 {
 520 //    MemDebug::cacheProbe(pkt);
 521     if (!pkt->req->isUncacheable()) {
 522         if (pkt->isInvalidate() && !pkt->isRead()
 523             && !pkt->isWrite()) {
 524             //Upgrade or Invalidate, satisfy it, don't forward
 525             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 526                     pkt->getAddr() & (((ULL(1))<<48)-1),
 527                     pkt->getAddr() & ~((Addr)blkSize - 1));
 528             pkt->flags |= SATISFIED;
 529             return 0;
 530         }
 531     }
 532
 533     PacketList writebacks;
 534     int lat;
 535     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 536
 537     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 538             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 539             pkt->getAddr() & ~((Addr)blkSize - 1));
 540
 541     if (!blk) {
 542         // Need to check for outstanding misses and writes
 543         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 544
 545         // There can only be one matching outstanding miss.
 546         MSHR* mshr = missQueue->findMSHR(blk_addr);
 547
 548         // There can be many matching outstanding writes.
 549         std::vector<MSHR*> writes;
 550         missQueue->findWrites(blk_addr, writes);
 551
 552         if (!update) {
 553                 otherSidePort->sendFunctional(pkt);
 554
 555             // Check for data in MSHR and writebuffer.
 556             if (mshr) {
 557                 warn("Found outstanding miss on an non-update probe");
 558                 MSHR::TargetList *targets = mshr->getTargetList();
 559                 MSHR::TargetList::iterator i = targets->begin();
 560                 MSHR::TargetList::iterator end = targets->end();
 561                 for (; i != end; ++i) {
 562                     Packet * target = *i;
 563                     // If the target contains data, and it overlaps the
 564                     // probed request, need to update data
 565                     if (target->isWrite() && target->intersect(pkt)) {
 566                         uint8_t* pkt_data;
 567                         uint8_t* write_data;
 568                         int data_size;
 569                         if (target->getAddr() < pkt->getAddr()) {
 570                             int offset = pkt->getAddr() - target->getAddr();
 571                             pkt_data = pkt->getPtr<uint8_t>();
 572                             write_data = target->getPtr<uint8_t>() + offset;
 573                             data_size = target->getSize() - offset;
 574                             assert(data_size > 0);
 575                             if (data_size > pkt->getSize())
 576                                 data_size = pkt->getSize();
 577                         } else {
 578                             int offset = target->getAddr() - pkt->getAddr();
 579                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 580                             write_data = target->getPtr<uint8_t>();
 581                             data_size = pkt->getSize() - offset;
 582                             assert(data_size > pkt->getSize());
 583                             if (data_size > target->getSize())
 584                                 data_size = target->getSize();
 585                         }
 586
 587                         if (pkt->isWrite()) {
 588                             memcpy(pkt_data, write_data, data_size);
 589                         } else {
 590                             memcpy(write_data, pkt_data, data_size);
 591                         }
 592                     }
 593                 }
 594             }
 595             for (int i = 0; i < writes.size(); ++i) {
 596                 Packet * write = writes[i]->pkt;
 597                 if (write->intersect(pkt)) {
 598                     warn("Found outstanding write on an non-update probe");
 599                     uint8_t* pkt_data;
 600                     uint8_t* write_data;
 601                     int data_size;
 602                     if (write->getAddr() < pkt->getAddr()) {
 603                         int offset = pkt->getAddr() - write->getAddr();
 604                         pkt_data = pkt->getPtr<uint8_t>();
 605                         write_data = write->getPtr<uint8_t>() + offset;
 606                         data_size = write->getSize() - offset;
 607                         assert(data_size > 0);
 608                         if (data_size > pkt->getSize())
 609                             data_size = pkt->getSize();
 610                     } else {
 611                         int offset = write->getAddr() - pkt->getAddr();
 612                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 613                         write_data = write->getPtr<uint8_t>();
 614                         data_size = pkt->getSize() - offset;
 615                         assert(data_size > pkt->getSize());
 616                         if (data_size > write->getSize())
 617                             data_size = write->getSize();
 618                     }
 619
 620                     if (pkt->isWrite()) {
 621                         memcpy(pkt_data, write_data, data_size);
 622                     } else {
 623                         memcpy(write_data, pkt_data, data_size);
 624                     }
 625
 626                 }
 627             }
 628             return 0;
 629         } else {
 630             // update the cache state and statistics
 631             if (mshr || !writes.empty()){
 632                 // Can't handle it, return pktuest unsatisfied.
 633                 panic("Atomic access ran into outstanding MSHR's or WB's!");
 634             }
 635             if (!pkt->req->isUncacheable()) {
 636                 // Fetch the cache block to fill
 637                 BlkType *blk = tags->findBlock(pkt);
 638                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 639                                                    (blk)? blk->status : 0);
 640
 641                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 642
 643                 busPkt->allocate();
 644
 645                 busPkt->time = curTick;
 646
 647                 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
 648                         busPkt->cmdString(),
 649                         busPkt->getAddr() & (((ULL(1))<<48)-1),
 650                         busPkt->getAddr() & ~((Addr)blkSize - 1));
 651
 652                 lat = memSidePort->sendAtomic(busPkt);
 653
 654                 //Be sure to flip the response to a request for coherence
 655                 if (busPkt->needsResponse()) {
 656                     busPkt->makeAtomicResponse();
 657                 }
 658
 659 /*              if (!(busPkt->flags & SATISFIED)) {
 660                     // blocked at a higher level, just return
 661                     return 0;
 662                 }
 663
 664 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 665
 666                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 667                 CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
 668                     DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
 669                             busPkt->cmdString(),
 670                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
 671                 if (old_state != new_state)
 672                     DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 673                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 674
 675                 tags->handleFill(blk, busPkt,
 676                                  new_state,
 677                                  writebacks, pkt);
 678                 //Free the packet
 679                 delete busPkt;
 680
 681                 // Handle writebacks if needed
 682                 while (!writebacks.empty()){
 683                     Packet *wbPkt = writebacks.front();
 684                     memSidePort->sendAtomic(wbPkt);
 685                     writebacks.pop_front();
 686                     delete wbPkt;
 687                 }
 688                 return lat + hitLatency;
 689             } else {
 690                 return memSidePort->sendAtomic(pkt);
 691             }
 692         }
 693     } else {
 694         // There was a cache hit.
 695         // Handle writebacks if needed
 696         while (!writebacks.empty()){
 697             memSidePort->sendAtomic(writebacks.front());
 698             writebacks.pop_front();
 699         }
 700
 701         if (update) {
 702             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 703         } else if (pkt->isWrite()) {
 704             // Still need to change data in all locations.
 705             otherSidePort->sendFunctional(pkt);
 706         }
 707         return hitLatency;
 708     }
 709     fatal("Probe not handled.\n");
 710     return 0;
 711 }
 712
 713 template<class TagStore, class Buffering, class Coherence>
 714 Tick
 715 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 716 {
 717         Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 718         BlkType *blk = tags->findBlock(pkt);
 719         MSHR *mshr = missQueue->findMSHR(blk_addr);
 720         CacheBlk::State new_state = 0;
 721         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 722         if (satisfy) {
 723             DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 724                     "new state is %i\n",
 725                     pkt->cmdString(), blk_addr, new_state);
 726
 727             tags->handleSnoop(blk, new_state, pkt);
 728             return hitLatency;
 729         }
 730         if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 731                      pkt->cmdString(), blk_addr, new_state);
 732         tags->handleSnoop(blk, new_state);
 733         return 0;
 734 }
 735