src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(Packet *pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         //Temporary solution to LL/SC
  90         if (pkt->isWrite() && (pkt->req->isLocked())) {
  91             pkt->req->setScResult(1);
  92         }
  93
  94         probe(pkt, true, NULL);
  95         //TEMP ALWAYS SUCCES FOR NOW
  96         pkt->result = Packet::Success;
  97     }
  98     else
  99     {
 100         if (pkt->isResponse())
 101             handleResponse(pkt);
 102         else
 103             return snoopProbe(pkt);
 104     }
 105     //Fix this timing info
 106     return hitLatency;
 107 }
 108
 109 template<class TagStore, class Buffering, class Coherence>
 110 void
 111 Cache<TagStore,Buffering,Coherence>::
 112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 113 {
 114     if (isCpuSide)
 115     {
 116         //TEMP USE CPU?THREAD 0 0
 117         pkt->req->setThreadContext(0,0);
 118
 119         //Temporary solution to LL/SC
 120         if (pkt->isWrite() && (pkt->req->isLocked())) {
 121             assert("Can't handle LL/SC on functional path\n");
 122         }
 123
 124         probe(pkt, false, memSidePort);
 125         //TEMP ALWAYS SUCCESFUL FOR NOW
 126         pkt->result = Packet::Success;
 127     }
 128     else
 129     {
 130             probe(pkt, false, cpuSidePort);
 131     }
 132 }
 133
 134 template<class TagStore, class Buffering, class Coherence>
 135 void
 136 Cache<TagStore,Buffering,Coherence>::
 137 recvStatusChange(Port::Status status, bool isCpuSide)
 138 {
 139
 140 }
 141
 142
 143 template<class TagStore, class Buffering, class Coherence>
 144 Cache<TagStore,Buffering,Coherence>::
 145 Cache(const std::string &_name,
 146       Cache<TagStore,Buffering,Coherence>::Params &params)
 147     : BaseCache(_name, params.baseParams),
 148       prefetchAccess(params.prefetchAccess),
 149       tags(params.tags), missQueue(params.missQueue),
 150       coherence(params.coherence), prefetcher(params.prefetcher),
 151       hitLatency(params.hitLatency)
 152 {
 153     tags->setCache(this);
 154     tags->setPrefetcher(prefetcher);
 155     missQueue->setCache(this);
 156     missQueue->setPrefetcher(prefetcher);
 157     coherence->setCache(this);
 158     prefetcher->setCache(this);
 159     prefetcher->setTags(tags);
 160     prefetcher->setBuffer(missQueue);
 161     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 162     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 163 }
 164
 165 template<class TagStore, class Buffering, class Coherence>
 166 void
 167 Cache<TagStore,Buffering,Coherence>::regStats()
 168 {
 169     BaseCache::regStats();
 170     tags->regStats(name());
 171     missQueue->regStats(name());
 172     coherence->regStats(name());
 173     prefetcher->regStats(name());
 174 }
 175
 176 template<class TagStore, class Buffering, class Coherence>
 177 bool
 178 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 179 {
 180 //@todo Add back in MemDebug Calls
 181 //    MemDebug::cacheAccess(pkt);
 182     BlkType *blk = NULL;
 183     PacketList writebacks;
 184     int size = blkSize;
 185     int lat = hitLatency;
 186     if (prefetchAccess) {
 187         //We are determining prefetches on access stream, call prefetcher
 188         prefetcher->handleMiss(pkt, curTick);
 189     }
 190     if (!pkt->req->isUncacheable()) {
 191         blk = tags->handleAccess(pkt, lat, writebacks);
 192     } else {
 193         size = pkt->getSize();
 194     }
 195     // If this is a block size write/hint (WH64) allocate the block here
 196     // if the coherence protocol allows it.
 197     /** @todo make the fast write alloc (wh64) work with coherence. */
 198     /** @todo Do we want to do fast writes for writebacks as well? */
 199     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 200         (pkt->cmd == Packet::WriteReq
 201          || pkt->cmd == Packet::WriteInvalidateReq) ) {
 202         // not outstanding misses, can do this
 203         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 204         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 205             if (outstanding_miss) {
 206                 warn("WriteInv doing a fastallocate"
 207                      "with an outstanding miss to the same address\n");
 208             }
 209             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 210                                    writebacks);
 211             ++fastWrites;
 212         }
 213     }
 214     while (!writebacks.empty()) {
 215         missQueue->doWriteback(writebacks.front());
 216         writebacks.pop_front();
 217     }
 218     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 219             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 220             pkt->getAddr() & ~((Addr)blkSize - 1));
 221     if (blk) {
 222         // Hit
 223         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 224         // clear dirty bit if write through
 225         if (pkt->needsResponse())
 226             respond(pkt, curTick+lat);
 227         if (pkt->cmd == Packet::Writeback) {
 228             //Signal that you can kill the pkt/req
 229             pkt->flags |= SATISFIED;
 230         }
 231         return true;
 232     }
 233
 234     // Miss
 235     if (!pkt->req->isUncacheable()) {
 236         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 237         /** @todo Move miss count code into BaseCache */
 238         if (missCount) {
 239             --missCount;
 240             if (missCount == 0)
 241                 exitSimLoop("A cache reached the maximum miss count");
 242         }
 243     }
 244     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 245 //    return MA_CACHE_MISS;
 246     return true;
 247 }
 248
 249
 250 template<class TagStore, class Buffering, class Coherence>
 251 Packet *
 252 Cache<TagStore,Buffering,Coherence>::getPacket()
 253 {
 254     assert(missQueue->havePending());
 255     Packet * pkt = missQueue->getPacket();
 256     if (pkt) {
 257         if (!pkt->req->isUncacheable()) {
 258             if (pkt->cmd == Packet::HardPFReq)
 259                 misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 260             BlkType *blk = tags->findBlock(pkt);
 261             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 262                                               (blk)? blk->status : 0);
 263             missQueue->setBusCmd(pkt, cmd);
 264         }
 265     }
 266
 267     assert(!doMasterRequest() || missQueue->havePending());
 268     assert(!pkt || pkt->time <= curTick);
 269     return pkt;
 270 }
 271
 272 template<class TagStore, class Buffering, class Coherence>
 273 void
 274 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
 275                                                 bool success)
 276 {
 277     if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
 278         if (!mshr->pkt->needsResponse()
 279             && !(mshr->pkt->cmd == Packet::UpgradeReq)
 280             && (pkt && (pkt->flags & SATISFIED))) {
 281             //Writeback, clean up the non copy version of the packet
 282             delete pkt;
 283         }
 284         missQueue->markInService(mshr->pkt, mshr);
 285         //Temp Hack for UPGRADES
 286         if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) {
 287             assert(pkt);  //Upgrades need to be fixed
 288             pkt->flags &= ~CACHE_LINE_FILL;
 289             BlkType *blk = tags->findBlock(pkt);
 290             CacheBlk::State old_state = (blk) ? blk->status : 0;
 291             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 292             if (old_state != new_state)
 293                 DPRINTF(Cache, "Block for blk addr %x moving from "
 294                         "state %i to %i\n",
 295                         pkt->getAddr() & (((ULL(1))<<48)-1),
 296                         old_state, new_state);
 297             //Set the state on the upgrade
 298             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 299             PacketList writebacks;
 300             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 301             assert(writebacks.empty());
 302             missQueue->handleResponse(pkt, curTick + hitLatency);
 303         }
 304     } else if (pkt && !pkt->req->isUncacheable()) {
 305         pkt->flags &= ~NACKED_LINE;
 306         pkt->flags &= ~SATISFIED;
 307         pkt->flags &= ~SNOOP_COMMIT;
 308
 309 //Rmove copy from mshr
 310         delete mshr->pkt;
 311         mshr->pkt = pkt;
 312
 313         missQueue->restoreOrigCmd(pkt);
 314     }
 315 }
 316
 317 template<class TagStore, class Buffering, class Coherence>
 318 void
 319 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 320 {
 321     BlkType *blk = NULL;
 322     if (pkt->senderState) {
 323         //Delete temp copy in MSHR, restore it.
 324         delete ((MSHR*)pkt->senderState)->pkt;
 325         ((MSHR*)pkt->senderState)->pkt = pkt;
 326         if (pkt->result == Packet::Nacked) {
 327             //pkt->reinitFromRequest();
 328             warn("NACKs from devices not connected to the same bus "
 329                  "not implemented\n");
 330             return;
 331         }
 332         if (pkt->result == Packet::BadAddress) {
 333             //Make the response a Bad address and send it
 334         }
 335 //      MemDebug::cacheResponse(pkt);
 336         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 337                 pkt->getAddr() & (((ULL(1))<<48)-1));
 338
 339         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 340             blk = tags->findBlock(pkt);
 341             CacheBlk::State old_state = (blk) ? blk->status : 0;
 342             PacketList writebacks;
 343             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 344             if (old_state != new_state)
 345                 DPRINTF(Cache, "Block for blk addr %x moving from "
 346                         "state %i to %i\n",
 347                         pkt->getAddr() & (((ULL(1))<<48)-1),
 348                         old_state, new_state);
 349             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 350                                    new_state, writebacks, pkt);
 351             while (!writebacks.empty()) {
 352                     missQueue->doWriteback(writebacks.front());
 353                     writebacks.pop_front();
 354             }
 355         }
 356         missQueue->handleResponse(pkt, curTick + hitLatency);
 357     }
 358 }
 359
 360 template<class TagStore, class Buffering, class Coherence>
 361 Packet *
 362 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 363 {
 364     return coherence->getPacket();
 365 }
 366
 367 template<class TagStore, class Buffering, class Coherence>
 368 void
 369 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
 370                                                          MSHR *cshr,
 371                                                          bool success)
 372 {
 373     coherence->sendResult(pkt, cshr, success);
 374 }
 375
 376
 377 template<class TagStore, class Buffering, class Coherence>
 378 void
 379 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 380 {
 381     if (pkt->req->isUncacheable()) {
 382         //Can't get a hit on an uncacheable address
 383         //Revisit this for multi level coherence
 384         return;
 385     }
 386     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 387     BlkType *blk = tags->findBlock(pkt);
 388     MSHR *mshr = missQueue->findMSHR(blk_addr);
 389     if (coherence->hasProtocol()) { //@todo Move this into handle bus req
 390         //If we find an mshr, and it is in service, we need to NACK or
 391         //invalidate
 392         if (mshr) {
 393             if (mshr->inService) {
 394                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 395                     && (pkt->cmd != Packet::InvalidateReq
 396                         && pkt->cmd != Packet::WriteInvalidateReq)) {
 397                     //If the outstanding request was an invalidate
 398                     //(upgrade,readex,..)  Then we need to ACK the request
 399                     //until we get the data Also NACK if the outstanding
 400                     //request is not a cachefill (writeback)
 401                     assert(!(pkt->flags & SATISFIED));
 402                     pkt->flags |= SATISFIED;
 403                     pkt->flags |= NACKED_LINE;
 404                     ///@todo NACK's from other levels
 405                     //warn("NACKs from devices not connected to the same bus "
 406                     //"not implemented\n");
 407                     //respondToSnoop(pkt, curTick + hitLatency);
 408                     return;
 409                 }
 410                 else {
 411                     //The supplier will be someone else, because we are
 412                     //waiting for the data.  This should cause this cache to
 413                     //be forced to go to the shared state, not the exclusive
 414                     //even though the shared line won't be asserted.  But for
 415                     //now we will just invlidate ourselves and allow the other
 416                     //cache to go into the exclusive state.  @todo Make it so
 417                     //a read to a pending read doesn't invalidate.  @todo Make
 418                     //it so that a read to a pending read can't be exclusive
 419                     //now.
 420
 421                     //Set the address so find match works
 422                     //panic("Don't have invalidates yet\n");
 423                     invalidatePkt->addrOverride(pkt->getAddr());
 424
 425                     //Append the invalidate on
 426                     missQueue->addTarget(mshr,invalidatePkt);
 427                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n",
 428                             pkt->getAddr() & (((ULL(1))<<48)-1));
 429                     return;
 430                 }
 431             }
 432         }
 433         //We also need to check the writeback buffers and handle those
 434         std::vector<MSHR *> writebacks;
 435         if (missQueue->findWrites(blk_addr, writebacks)) {
 436             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n",
 437                     pkt->getAddr() & (((ULL(1))<<48)-1));
 438
 439             //Look through writebacks for any non-uncachable writes, use that
 440             for (int i=0; i<writebacks.size(); i++) {
 441                 mshr = writebacks[i];
 442
 443                 if (!mshr->pkt->req->isUncacheable()) {
 444                     if (pkt->isRead()) {
 445                         //Only Upgrades don't get here
 446                         //Supply the data
 447                         assert(!(pkt->flags & SATISFIED));
 448                         pkt->flags |= SATISFIED;
 449
 450                         //If we are in an exclusive protocol, make it ask again
 451                         //to get write permissions (upgrade), signal shared
 452                         pkt->flags |= SHARED_LINE;
 453
 454                         assert(pkt->isRead());
 455                         Addr offset = pkt->getAddr() & (blkSize - 1);
 456                         assert(offset < blkSize);
 457                         assert(pkt->getSize() <= blkSize);
 458                         assert(offset + pkt->getSize() <=blkSize);
 459                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 460
 461                         respondToSnoop(pkt, curTick + hitLatency);
 462                     }
 463
 464                     if (pkt->isInvalidate()) {
 465                         //This must be an upgrade or other cache will take
 466                         //ownership
 467                         missQueue->markInService(mshr->pkt, mshr);
 468                     }
 469                     return;
 470                 }
 471             }
 472         }
 473     }
 474     CacheBlk::State new_state;
 475     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 476     if (satisfy) {
 477         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 478                 "now supplying data, new state is %i\n",
 479                 pkt->cmdString(), blk_addr, new_state);
 480
 481         tags->handleSnoop(blk, new_state, pkt);
 482         respondToSnoop(pkt, curTick + hitLatency);
 483         return;
 484     }
 485     if (blk)
 486         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 487                 "new state is %i\n", pkt->cmdString(), blk_addr, new_state);
 488     tags->handleSnoop(blk, new_state);
 489 }
 490
 491 template<class TagStore, class Buffering, class Coherence>
 492 void
 493 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 494 {
 495     //Need to handle the response, if NACKED
 496     if (pkt->flags & NACKED_LINE) {
 497         //Need to mark it as not in service, and retry for bus
 498         assert(0); //Yeah, we saw a NACK come through
 499
 500         //For now this should never get called, we return false when we see a
 501         //NACK instead, by doing this we allow the bus_blocked mechanism to
 502         //handle the retry For now it retrys in just 2 cycles, need to figure
 503         //out how to change that Eventually we will want to also have success
 504         //come in as a parameter Need to make sure that we handle the
 505         //functionality that happens on successufl return of the sendAddr
 506         //function
 507     }
 508 }
 509
 510 template<class TagStore, class Buffering, class Coherence>
 511 void
 512 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 513 {
 514     tags->invalidateBlk(addr);
 515 }
 516
 517
 518 /**
 519  * @todo Fix to not assume write allocate
 520  */
 521 template<class TagStore, class Buffering, class Coherence>
 522 Tick
 523 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
 524                                            CachePort* otherSidePort)
 525 {
 526 //    MemDebug::cacheProbe(pkt);
 527     if (!pkt->req->isUncacheable()) {
 528         if (pkt->isInvalidate() && !pkt->isRead()
 529             && !pkt->isWrite()) {
 530             //Upgrade or Invalidate, satisfy it, don't forward
 531             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 532                     pkt->getAddr() & (((ULL(1))<<48)-1),
 533                     pkt->getAddr() & ~((Addr)blkSize - 1));
 534             pkt->flags |= SATISFIED;
 535             return 0;
 536         }
 537     }
 538
 539     PacketList writebacks;
 540     int lat;
 541     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 542
 543     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 544             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 545             pkt->getAddr() & ~((Addr)blkSize - 1));
 546
 547     if (!blk) {
 548         // Need to check for outstanding misses and writes
 549         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 550
 551         // There can only be one matching outstanding miss.
 552         MSHR* mshr = missQueue->findMSHR(blk_addr);
 553
 554         // There can be many matching outstanding writes.
 555         std::vector<MSHR*> writes;
 556         missQueue->findWrites(blk_addr, writes);
 557
 558         if (!update) {
 559                 otherSidePort->sendFunctional(pkt);
 560
 561             // Check for data in MSHR and writebuffer.
 562             if (mshr) {
 563                 warn("Found outstanding miss on an non-update probe");
 564                 MSHR::TargetList *targets = mshr->getTargetList();
 565                 MSHR::TargetList::iterator i = targets->begin();
 566                 MSHR::TargetList::iterator end = targets->end();
 567                 for (; i != end; ++i) {
 568                     Packet * target = *i;
 569                     // If the target contains data, and it overlaps the
 570                     // probed request, need to update data
 571                     if (target->isWrite() && target->intersect(pkt)) {
 572                         uint8_t* pkt_data;
 573                         uint8_t* write_data;
 574                         int data_size;
 575                         if (target->getAddr() < pkt->getAddr()) {
 576                             int offset = pkt->getAddr() - target->getAddr();
 577                             pkt_data = pkt->getPtr<uint8_t>();
 578                             write_data = target->getPtr<uint8_t>() + offset;
 579                             data_size = target->getSize() - offset;
 580                             assert(data_size > 0);
 581                             if (data_size > pkt->getSize())
 582                                 data_size = pkt->getSize();
 583                         } else {
 584                             int offset = target->getAddr() - pkt->getAddr();
 585                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 586                             write_data = target->getPtr<uint8_t>();
 587                             data_size = pkt->getSize() - offset;
 588                             assert(data_size > pkt->getSize());
 589                             if (data_size > target->getSize())
 590                                 data_size = target->getSize();
 591                         }
 592
 593                         if (pkt->isWrite()) {
 594                             memcpy(pkt_data, write_data, data_size);
 595                         } else {
 596                             memcpy(write_data, pkt_data, data_size);
 597                         }
 598                     }
 599                 }
 600             }
 601             for (int i = 0; i < writes.size(); ++i) {
 602                 Packet * write = writes[i]->pkt;
 603                 if (write->intersect(pkt)) {
 604                     warn("Found outstanding write on an non-update probe");
 605                     uint8_t* pkt_data;
 606                     uint8_t* write_data;
 607                     int data_size;
 608                     if (write->getAddr() < pkt->getAddr()) {
 609                         int offset = pkt->getAddr() - write->getAddr();
 610                         pkt_data = pkt->getPtr<uint8_t>();
 611                         write_data = write->getPtr<uint8_t>() + offset;
 612                         data_size = write->getSize() - offset;
 613                         assert(data_size > 0);
 614                         if (data_size > pkt->getSize())
 615                             data_size = pkt->getSize();
 616                     } else {
 617                         int offset = write->getAddr() - pkt->getAddr();
 618                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 619                         write_data = write->getPtr<uint8_t>();
 620                         data_size = pkt->getSize() - offset;
 621                         assert(data_size > pkt->getSize());
 622                         if (data_size > write->getSize())
 623                             data_size = write->getSize();
 624                     }
 625
 626                     if (pkt->isWrite()) {
 627                         memcpy(pkt_data, write_data, data_size);
 628                     } else {
 629                         memcpy(write_data, pkt_data, data_size);
 630                     }
 631
 632                 }
 633             }
 634             return 0;
 635         } else {
 636             // update the cache state and statistics
 637             if (mshr || !writes.empty()){
 638                 // Can't handle it, return pktuest unsatisfied.
 639                 panic("Atomic access ran into outstanding MSHR's or WB's!");
 640             }
 641             if (!pkt->req->isUncacheable()) {
 642                 // Fetch the cache block to fill
 643                 BlkType *blk = tags->findBlock(pkt);
 644                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 645                                                    (blk)? blk->status : 0);
 646
 647                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 648
 649                 busPkt->allocate();
 650
 651                 busPkt->time = curTick;
 652
 653                 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
 654                         busPkt->cmdString(),
 655                         busPkt->getAddr() & (((ULL(1))<<48)-1),
 656                         busPkt->getAddr() & ~((Addr)blkSize - 1));
 657
 658                 lat = memSidePort->sendAtomic(busPkt);
 659
 660                 //Be sure to flip the response to a request for coherence
 661                 if (busPkt->needsResponse()) {
 662                     busPkt->makeAtomicResponse();
 663                 }
 664
 665 /*              if (!(busPkt->flags & SATISFIED)) {
 666                     // blocked at a higher level, just return
 667                     return 0;
 668                 }
 669
 670 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 671
 672                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 673                 CacheBlk::State new_state =
 674                     coherence->getNewState(busPkt, old_state);
 675                 DPRINTF(Cache,
 676                         "Receive response:%s for blk addr %x in state %i\n",
 677                         busPkt->cmdString(),
 678                         busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
 679                 if (old_state != new_state)
 680                     DPRINTF(Cache, "Block for blk addr %x moving from "
 681                             "state %i to %i\n",
 682                             busPkt->getAddr() & (((ULL(1))<<48)-1),
 683                             old_state, new_state);
 684
 685                 tags->handleFill(blk, busPkt,
 686                                  new_state,
 687                                  writebacks, pkt);
 688                 //Free the packet
 689                 delete busPkt;
 690
 691                 // Handle writebacks if needed
 692                 while (!writebacks.empty()){
 693                     Packet *wbPkt = writebacks.front();
 694                     memSidePort->sendAtomic(wbPkt);
 695                     writebacks.pop_front();
 696                     delete wbPkt;
 697                 }
 698                 return lat + hitLatency;
 699             } else {
 700                 return memSidePort->sendAtomic(pkt);
 701             }
 702         }
 703     } else {
 704         // There was a cache hit.
 705         // Handle writebacks if needed
 706         while (!writebacks.empty()){
 707             memSidePort->sendAtomic(writebacks.front());
 708             writebacks.pop_front();
 709         }
 710
 711         if (update) {
 712             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 713         } else if (pkt->isWrite()) {
 714             // Still need to change data in all locations.
 715             otherSidePort->sendFunctional(pkt);
 716         }
 717         return hitLatency;
 718     }
 719     fatal("Probe not handled.\n");
 720     return 0;
 721 }
 722
 723 template<class TagStore, class Buffering, class Coherence>
 724 Tick
 725 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 726 {
 727         Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 728         BlkType *blk = tags->findBlock(pkt);
 729         MSHR *mshr = missQueue->findMSHR(blk_addr);
 730         CacheBlk::State new_state = 0;
 731         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 732         if (satisfy) {
 733             DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 734                     "now supplying data, new state is %i\n",
 735                     pkt->cmdString(), blk_addr, new_state);
 736
 737             tags->handleSnoop(blk, new_state, pkt);
 738             return hitLatency;
 739         }
 740         if (blk)
 741             DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 742                     "new state is %i\n",
 743                     pkt->cmdString(), blk_addr, new_state);
 744         tags->handleSnoop(blk, new_state);
 745         return 0;
 746 }
 747