src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(Packet *pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         //Temporary solution to LL/SC
  90         if (pkt->isWrite() && (pkt->req->isLocked())) {
  91             pkt->req->setScResult(1);
  92         }
  93
  94         probe(pkt, true, NULL);
  95         //TEMP ALWAYS SUCCES FOR NOW
  96         pkt->result = Packet::Success;
  97     }
  98     else
  99     {
 100         if (pkt->isResponse())
 101             handleResponse(pkt);
 102         else
 103             return snoopProbe(pkt);
 104     }
 105     //Fix this timing info
 106     return hitLatency;
 107 }
 108
 109 template<class TagStore, class Buffering, class Coherence>
 110 void
 111 Cache<TagStore,Buffering,Coherence>::
 112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 113 {
 114     if (isCpuSide)
 115     {
 116         //TEMP USE CPU?THREAD 0 0
 117         pkt->req->setThreadContext(0,0);
 118
 119         //Temporary solution to LL/SC
 120         if (pkt->isWrite() && (pkt->req->isLocked())) {
 121             assert("Can't handle LL/SC on functional path\n");
 122         }
 123
 124         probe(pkt, false, memSidePort);
 125         //TEMP ALWAYS SUCCESFUL FOR NOW
 126         pkt->result = Packet::Success;
 127     }
 128     else
 129     {
 130             probe(pkt, false, cpuSidePort);
 131     }
 132 }
 133
 134 template<class TagStore, class Buffering, class Coherence>
 135 void
 136 Cache<TagStore,Buffering,Coherence>::
 137 recvStatusChange(Port::Status status, bool isCpuSide)
 138 {
 139
 140 }
 141
 142
 143 template<class TagStore, class Buffering, class Coherence>
 144 Cache<TagStore,Buffering,Coherence>::
 145 Cache(const std::string &_name,
 146       Cache<TagStore,Buffering,Coherence>::Params &params)
 147     : BaseCache(_name, params.baseParams),
 148       prefetchAccess(params.prefetchAccess),
 149       tags(params.tags), missQueue(params.missQueue),
 150       coherence(params.coherence), prefetcher(params.prefetcher),
 151       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
 152       hitLatency(params.hitLatency)
 153 {
 154     tags->setCache(this);
 155     tags->setPrefetcher(prefetcher);
 156     missQueue->setCache(this);
 157     missQueue->setPrefetcher(prefetcher);
 158     coherence->setCache(this);
 159     prefetcher->setCache(this);
 160     prefetcher->setTags(tags);
 161     prefetcher->setBuffer(missQueue);
 162     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 163     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 164 }
 165
 166 template<class TagStore, class Buffering, class Coherence>
 167 void
 168 Cache<TagStore,Buffering,Coherence>::regStats()
 169 {
 170     BaseCache::regStats();
 171     tags->regStats(name());
 172     missQueue->regStats(name());
 173     coherence->regStats(name());
 174     prefetcher->regStats(name());
 175 }
 176
 177 template<class TagStore, class Buffering, class Coherence>
 178 bool
 179 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 180 {
 181 //@todo Add back in MemDebug Calls
 182 //    MemDebug::cacheAccess(pkt);
 183     BlkType *blk = NULL;
 184     PacketList writebacks;
 185     int size = blkSize;
 186     int lat = hitLatency;
 187     if (prefetchAccess) {
 188         //We are determining prefetches on access stream, call prefetcher
 189         prefetcher->handleMiss(pkt, curTick);
 190     }
 191     if (!pkt->req->isUncacheable()) {
 192         blk = tags->handleAccess(pkt, lat, writebacks);
 193     } else {
 194         size = pkt->getSize();
 195     }
 196     // If this is a block size write/hint (WH64) allocate the block here
 197     // if the coherence protocol allows it.
 198     /** @todo make the fast write alloc (wh64) work with coherence. */
 199     /** @todo Do we want to do fast writes for writebacks as well? */
 200     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 201         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 202         // not outstanding misses, can do this
 203         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 204         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 205             if (outstanding_miss) {
 206                 warn("WriteInv doing a fastallocate"
 207                      "with an outstanding miss to the same address\n");
 208             }
 209             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 210                                    writebacks);
 211             ++fastWrites;
 212         }
 213     }
 214     while (!writebacks.empty()) {
 215         missQueue->doWriteback(writebacks.front());
 216         writebacks.pop_front();
 217     }
 218     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 219             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 220             pkt->getAddr() & ~((Addr)blkSize - 1));
 221     if (blk) {
 222         // Hit
 223         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 224         // clear dirty bit if write through
 225         if (pkt->needsResponse())
 226             respond(pkt, curTick+lat);
 227         if (pkt->cmd == Packet::Writeback) {
 228             //Signal that you can kill the pkt/req
 229             pkt->flags |= SATISFIED;
 230         }
 231         return true;
 232     }
 233
 234     // Miss
 235     if (!pkt->req->isUncacheable()) {
 236         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 237         /** @todo Move miss count code into BaseCache */
 238         if (missCount) {
 239             --missCount;
 240             if (missCount == 0)
 241                 exitSimLoop("A cache reached the maximum miss count");
 242         }
 243     }
 244     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 245 //    return MA_CACHE_MISS;
 246     return true;
 247 }
 248
 249
 250 template<class TagStore, class Buffering, class Coherence>
 251 Packet *
 252 Cache<TagStore,Buffering,Coherence>::getPacket()
 253 {
 254     assert(missQueue->havePending());
 255     Packet * pkt = missQueue->getPacket();
 256     if (pkt) {
 257         if (!pkt->req->isUncacheable()) {
 258             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 259             BlkType *blk = tags->findBlock(pkt);
 260             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 261                                               (blk)? blk->status : 0);
 262             missQueue->setBusCmd(pkt, cmd);
 263         }
 264     }
 265
 266     assert(!doMasterRequest() || missQueue->havePending());
 267     assert(!pkt || pkt->time <= curTick);
 268     return pkt;
 269 }
 270
 271 template<class TagStore, class Buffering, class Coherence>
 272 void
 273 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
 274 {
 275     if (success && !(pkt->flags & NACKED_LINE)) {
 276         missQueue->markInService(pkt, mshr);
 277         //Temp Hack for UPGRADES
 278         if (pkt->cmd == Packet::UpgradeReq) {
 279             pkt->flags &= ~CACHE_LINE_FILL;
 280             BlkType *blk = tags->findBlock(pkt);
 281             CacheBlk::State old_state = (blk) ? blk->status : 0;
 282             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 283             if (old_state != new_state)
 284                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 285                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 286             //Set the state on the upgrade
 287             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 288             PacketList writebacks;
 289             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 290             assert(writebacks.empty());
 291             missQueue->handleResponse(pkt, curTick + hitLatency);
 292         }
 293     } else if (pkt && !pkt->req->isUncacheable()) {
 294         pkt->flags &= ~NACKED_LINE;
 295         pkt->flags &= ~SATISFIED;
 296         pkt->flags &= ~SNOOP_COMMIT;
 297         missQueue->restoreOrigCmd(pkt);
 298     }
 299 }
 300
 301 template<class TagStore, class Buffering, class Coherence>
 302 void
 303 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 304 {
 305     BlkType *blk = NULL;
 306     if (pkt->senderState) {
 307         ((MSHR*)pkt->senderState)->pkt = pkt;
 308         if (pkt->result == Packet::Nacked) {
 309             //pkt->reinitFromRequest();
 310             warn("NACKs from devices not connected to the same bus not implemented\n");
 311             return;
 312         }
 313         if (pkt->result == Packet::BadAddress) {
 314             //Make the response a Bad address and send it
 315         }
 316 //      MemDebug::cacheResponse(pkt);
 317         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 318                 pkt->getAddr() & (((ULL(1))<<48)-1));
 319
 320         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 321             blk = tags->findBlock(pkt);
 322             CacheBlk::State old_state = (blk) ? blk->status : 0;
 323             PacketList writebacks;
 324             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 325             if (old_state != new_state)
 326                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 327                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 328             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 329                                    new_state, writebacks, pkt);
 330             while (!writebacks.empty()) {
 331                     missQueue->doWriteback(writebacks.front());
 332                     writebacks.pop_front();
 333             }
 334         }
 335         missQueue->handleResponse(pkt, curTick + hitLatency);
 336     }
 337 }
 338
 339 template<class TagStore, class Buffering, class Coherence>
 340 void
 341 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
 342 {
 343     // Need to temporarily move this blk into MSHRs
 344     MSHR *mshr = missQueue->allocateTargetList(addr);
 345     int lat;
 346     PacketList dummy;
 347     // Read the data into the mshr
 348     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 349     assert(dummy.empty());
 350     assert(mshr->pkt->flags & SATISFIED);
 351     // can overload order since it isn't used on non pending blocks
 352     mshr->order = blk->status;
 353     // temporarily remove the block from the cache.
 354     tags->invalidateBlk(addr);
 355 }
 356
 357 template<class TagStore, class Buffering, class Coherence>
 358 void
 359 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 360 {
 361     // Need to temporarily move this blk into MSHRs
 362     assert(mshr->pkt->cmd == Packet::ReadReq);
 363     int lat;
 364     PacketList dummy;
 365     // Read the data into the mshr
 366     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 367     assert(dummy.empty());
 368     assert(mshr->pkt->flags & SATISFIED);
 369     // can overload order since it isn't used on non pending blocks
 370     mshr->order = blk->status;
 371     // temporarily remove the block from the cache.
 372     tags->invalidateBlk(mshr->pkt->getAddr());
 373 }
 374
 375
 376 template<class TagStore, class Buffering, class Coherence>
 377 Packet *
 378 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 379 {
 380     return coherence->getPacket();
 381 }
 382
 383 template<class TagStore, class Buffering, class Coherence>
 384 void
 385 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
 386                                                          MSHR *cshr,
 387                                                          bool success)
 388 {
 389     coherence->sendResult(pkt, cshr, success);
 390 }
 391
 392
 393 template<class TagStore, class Buffering, class Coherence>
 394 void
 395 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 396 {
 397     if (pkt->req->isUncacheable()) {
 398         //Can't get a hit on an uncacheable address
 399         //Revisit this for multi level coherence
 400         return;
 401     }
 402     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 403     BlkType *blk = tags->findBlock(pkt);
 404     MSHR *mshr = missQueue->findMSHR(blk_addr);
 405     if (coherence->hasProtocol()) { //@todo Move this into handle bus req
 406         //If we find an mshr, and it is in service, we need to NACK or invalidate
 407         if (mshr) {
 408             if (mshr->inService) {
 409                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 410                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 411                     //If the outstanding request was an invalidate (upgrade,readex,..)
 412                     //Then we need to ACK the request until we get the data
 413                     //Also NACK if the outstanding request is not a cachefill (writeback)
 414                     assert(!(pkt->flags & SATISFIED));
 415                     pkt->flags |= SATISFIED;
 416                     pkt->flags |= NACKED_LINE;
 417                     ///@todo NACK's from other levels
 418                     //warn("NACKs from devices not connected to the same bus not implemented\n");
 419                     //respondToSnoop(pkt, curTick + hitLatency);
 420                     return;
 421                 }
 422                 else {
 423                     //The supplier will be someone else, because we are waiting for
 424                     //the data.  This should cause this cache to be forced to go to
 425                     //the shared state, not the exclusive even though the shared line
 426                     //won't be asserted.  But for now we will just invlidate ourselves
 427                     //and allow the other cache to go into the exclusive state.
 428                     //@todo Make it so a read to a pending read doesn't invalidate.
 429                     //@todo Make it so that a read to a pending read can't be exclusive now.
 430
 431                     //Set the address so find match works
 432                     //panic("Don't have invalidates yet\n");
 433                     invalidatePkt->addrOverride(pkt->getAddr());
 434
 435                     //Append the invalidate on
 436                     missQueue->addTarget(mshr,invalidatePkt);
 437                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 438                     return;
 439                 }
 440             }
 441         }
 442         //We also need to check the writeback buffers and handle those
 443         std::vector<MSHR *> writebacks;
 444         if (missQueue->findWrites(blk_addr, writebacks)) {
 445             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 446
 447             //Look through writebacks for any non-uncachable writes, use that
 448             for (int i=0; i<writebacks.size(); i++) {
 449                 mshr = writebacks[i];
 450
 451                 if (!mshr->pkt->req->isUncacheable()) {
 452                     if (pkt->isRead()) {
 453                         //Only Upgrades don't get here
 454                         //Supply the data
 455                         assert(!(pkt->flags & SATISFIED));
 456                         pkt->flags |= SATISFIED;
 457
 458                         //If we are in an exclusive protocol, make it ask again
 459                         //to get write permissions (upgrade), signal shared
 460                         pkt->flags |= SHARED_LINE;
 461
 462                         assert(pkt->isRead());
 463                         Addr offset = pkt->getAddr() & (blkSize - 1);
 464                         assert(offset < blkSize);
 465                         assert(pkt->getSize() <= blkSize);
 466                         assert(offset + pkt->getSize() <=blkSize);
 467                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 468
 469                         respondToSnoop(pkt, curTick + hitLatency);
 470                     }
 471
 472                     if (pkt->isInvalidate()) {
 473                         //This must be an upgrade or other cache will take ownership
 474                         missQueue->markInService(mshr->pkt, mshr);
 475                     }
 476                     return;
 477                 }
 478             }
 479         }
 480     }
 481     CacheBlk::State new_state;
 482     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 483     if (satisfy) {
 484         DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 485                 "new state is %i\n",
 486                 pkt->cmdString(), blk_addr, new_state);
 487
 488         tags->handleSnoop(blk, new_state, pkt);
 489         respondToSnoop(pkt, curTick + hitLatency);
 490         return;
 491     }
 492     if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 493                      pkt->cmdString(), blk_addr, new_state);
 494     tags->handleSnoop(blk, new_state);
 495 }
 496
 497 template<class TagStore, class Buffering, class Coherence>
 498 void
 499 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 500 {
 501     //Need to handle the response, if NACKED
 502     if (pkt->flags & NACKED_LINE) {
 503         //Need to mark it as not in service, and retry for bus
 504         assert(0); //Yeah, we saw a NACK come through
 505
 506         //For now this should never get called, we return false when we see a NACK
 507         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 508         //For now it retrys in just 2 cycles, need to figure out how to change that
 509         //Eventually we will want to also have success come in as a parameter
 510         //Need to make sure that we handle the functionality that happens on successufl
 511         //return of the sendAddr function
 512     }
 513 }
 514
 515 template<class TagStore, class Buffering, class Coherence>
 516 void
 517 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 518 {
 519     tags->invalidateBlk(addr);
 520 }
 521
 522
 523 /**
 524  * @todo Fix to not assume write allocate
 525  */
 526 template<class TagStore, class Buffering, class Coherence>
 527 Tick
 528 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
 529 {
 530 //    MemDebug::cacheProbe(pkt);
 531     if (!pkt->req->isUncacheable()) {
 532         if (pkt->isInvalidate() && !pkt->isRead()
 533             && !pkt->isWrite()) {
 534             //Upgrade or Invalidate, satisfy it, don't forward
 535             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 536                     pkt->getAddr() & (((ULL(1))<<48)-1),
 537                     pkt->getAddr() & ~((Addr)blkSize - 1));
 538             pkt->flags |= SATISFIED;
 539             return 0;
 540         }
 541     }
 542
 543     PacketList writebacks;
 544     int lat;
 545     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 546
 547     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 548             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 549             pkt->getAddr() & ~((Addr)blkSize - 1));
 550
 551     if (!blk) {
 552         // Need to check for outstanding misses and writes
 553         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 554
 555         // There can only be one matching outstanding miss.
 556         MSHR* mshr = missQueue->findMSHR(blk_addr);
 557
 558         // There can be many matching outstanding writes.
 559         std::vector<MSHR*> writes;
 560         missQueue->findWrites(blk_addr, writes);
 561
 562         if (!update) {
 563                 otherSidePort->sendFunctional(pkt);
 564
 565             // Check for data in MSHR and writebuffer.
 566             if (mshr) {
 567                 warn("Found outstanding miss on an non-update probe");
 568                 MSHR::TargetList *targets = mshr->getTargetList();
 569                 MSHR::TargetList::iterator i = targets->begin();
 570                 MSHR::TargetList::iterator end = targets->end();
 571                 for (; i != end; ++i) {
 572                     Packet * target = *i;
 573                     // If the target contains data, and it overlaps the
 574                     // probed request, need to update data
 575                     if (target->isWrite() && target->intersect(pkt)) {
 576                         uint8_t* pkt_data;
 577                         uint8_t* write_data;
 578                         int data_size;
 579                         if (target->getAddr() < pkt->getAddr()) {
 580                             int offset = pkt->getAddr() - target->getAddr();
 581                             pkt_data = pkt->getPtr<uint8_t>();
 582                             write_data = target->getPtr<uint8_t>() + offset;
 583                             data_size = target->getSize() - offset;
 584                             assert(data_size > 0);
 585                             if (data_size > pkt->getSize())
 586                                 data_size = pkt->getSize();
 587                         } else {
 588                             int offset = target->getAddr() - pkt->getAddr();
 589                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 590                             write_data = target->getPtr<uint8_t>();
 591                             data_size = pkt->getSize() - offset;
 592                             assert(data_size > pkt->getSize());
 593                             if (data_size > target->getSize())
 594                                 data_size = target->getSize();
 595                         }
 596
 597                         if (pkt->isWrite()) {
 598                             memcpy(pkt_data, write_data, data_size);
 599                         } else {
 600                             memcpy(write_data, pkt_data, data_size);
 601                         }
 602                     }
 603                 }
 604             }
 605             for (int i = 0; i < writes.size(); ++i) {
 606                 Packet * write = writes[i]->pkt;
 607                 if (write->intersect(pkt)) {
 608                     warn("Found outstanding write on an non-update probe");
 609                     uint8_t* pkt_data;
 610                     uint8_t* write_data;
 611                     int data_size;
 612                     if (write->getAddr() < pkt->getAddr()) {
 613                         int offset = pkt->getAddr() - write->getAddr();
 614                         pkt_data = pkt->getPtr<uint8_t>();
 615                         write_data = write->getPtr<uint8_t>() + offset;
 616                         data_size = write->getSize() - offset;
 617                         assert(data_size > 0);
 618                         if (data_size > pkt->getSize())
 619                             data_size = pkt->getSize();
 620                     } else {
 621                         int offset = write->getAddr() - pkt->getAddr();
 622                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 623                         write_data = write->getPtr<uint8_t>();
 624                         data_size = pkt->getSize() - offset;
 625                         assert(data_size > pkt->getSize());
 626                         if (data_size > write->getSize())
 627                             data_size = write->getSize();
 628                     }
 629
 630                     if (pkt->isWrite()) {
 631                         memcpy(pkt_data, write_data, data_size);
 632                     } else {
 633                         memcpy(write_data, pkt_data, data_size);
 634                     }
 635
 636                 }
 637             }
 638             return 0;
 639         } else {
 640             // update the cache state and statistics
 641             if (mshr || !writes.empty()){
 642                 // Can't handle it, return pktuest unsatisfied.
 643                 panic("Atomic access ran into outstanding MSHR's or WB's!");
 644             }
 645             if (!pkt->req->isUncacheable()) {
 646                 // Fetch the cache block to fill
 647                 BlkType *blk = tags->findBlock(pkt);
 648                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 649                                                    (blk)? blk->status : 0);
 650
 651                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 652
 653                 busPkt->allocate();
 654
 655                 busPkt->time = curTick;
 656
 657                 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
 658                         busPkt->cmdString(),
 659                         busPkt->getAddr() & (((ULL(1))<<48)-1),
 660                         busPkt->getAddr() & ~((Addr)blkSize - 1));
 661
 662                 lat = memSidePort->sendAtomic(busPkt);
 663
 664                 //Be sure to flip the response to a request for coherence
 665                 if (busPkt->needsResponse()) {
 666                     busPkt->makeAtomicResponse();
 667                 }
 668
 669 /*              if (!(busPkt->flags & SATISFIED)) {
 670                     // blocked at a higher level, just return
 671                     return 0;
 672                 }
 673
 674 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 675
 676                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 677                 CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
 678                     DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
 679                             busPkt->cmdString(),
 680                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
 681                 if (old_state != new_state)
 682                     DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 683                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 684
 685                 tags->handleFill(blk, busPkt,
 686                                  new_state,
 687                                  writebacks, pkt);
 688                 //Free the packet
 689                 delete busPkt;
 690
 691                 // Handle writebacks if needed
 692                 while (!writebacks.empty()){
 693                     Packet *wbPkt = writebacks.front();
 694                     memSidePort->sendAtomic(wbPkt);
 695                     writebacks.pop_front();
 696                     delete wbPkt;
 697                 }
 698                 return lat + hitLatency;
 699             } else {
 700                 return memSidePort->sendAtomic(pkt);
 701             }
 702         }
 703     } else {
 704         // There was a cache hit.
 705         // Handle writebacks if needed
 706         while (!writebacks.empty()){
 707             memSidePort->sendAtomic(writebacks.front());
 708             writebacks.pop_front();
 709         }
 710
 711         if (update) {
 712             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 713         } else if (pkt->isWrite()) {
 714             // Still need to change data in all locations.
 715             otherSidePort->sendFunctional(pkt);
 716         }
 717         return hitLatency;
 718     }
 719     fatal("Probe not handled.\n");
 720     return 0;
 721 }
 722
 723 template<class TagStore, class Buffering, class Coherence>
 724 Tick
 725 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 726 {
 727         Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 728         BlkType *blk = tags->findBlock(pkt);
 729         MSHR *mshr = missQueue->findMSHR(blk_addr);
 730         CacheBlk::State new_state = 0;
 731         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 732         if (satisfy) {
 733             DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 734                     "new state is %i\n",
 735                     pkt->cmdString(), blk_addr, new_state);
 736
 737             tags->handleSnoop(blk, new_state, pkt);
 738             return hitLatency;
 739         }
 740         if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 741                      pkt->cmdString(), blk_addr, new_state);
 742         tags->handleSnoop(blk, new_state);
 743         return 0;
 744 }
 745