src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(Packet *pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         //Temporary solution to LL/SC
  90         if (pkt->isWrite() && (pkt->req->isLocked())) {
  91             pkt->req->setScResult(1);
  92         }
  93
  94         probe(pkt, true, NULL);
  95         //TEMP ALWAYS SUCCES FOR NOW
  96         pkt->result = Packet::Success;
  97     }
  98     else
  99     {
 100         if (pkt->isResponse())
 101             handleResponse(pkt);
 102         else
 103             return snoopProbe(pkt);
 104     }
 105     //Fix this timing info
 106     return hitLatency;
 107 }
 108
 109 template<class TagStore, class Buffering, class Coherence>
 110 void
 111 Cache<TagStore,Buffering,Coherence>::
 112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 113 {
 114     if (isCpuSide)
 115     {
 116         //TEMP USE CPU?THREAD 0 0
 117         pkt->req->setThreadContext(0,0);
 118
 119         //Temporary solution to LL/SC
 120         if (pkt->isWrite() && (pkt->req->isLocked())) {
 121             assert("Can't handle LL/SC on functional path\n");
 122         }
 123
 124         probe(pkt, false, memSidePort);
 125         //TEMP ALWAYS SUCCESFUL FOR NOW
 126         pkt->result = Packet::Success;
 127     }
 128     else
 129     {
 130             probe(pkt, false, cpuSidePort);
 131     }
 132 }
 133
 134 template<class TagStore, class Buffering, class Coherence>
 135 void
 136 Cache<TagStore,Buffering,Coherence>::
 137 recvStatusChange(Port::Status status, bool isCpuSide)
 138 {
 139
 140 }
 141
 142
 143 template<class TagStore, class Buffering, class Coherence>
 144 Cache<TagStore,Buffering,Coherence>::
 145 Cache(const std::string &_name,
 146       Cache<TagStore,Buffering,Coherence>::Params &params)
 147     : BaseCache(_name, params.baseParams),
 148       prefetchAccess(params.prefetchAccess),
 149       tags(params.tags), missQueue(params.missQueue),
 150       coherence(params.coherence), prefetcher(params.prefetcher),
 151       hitLatency(params.hitLatency)
 152 {
 153     tags->setCache(this);
 154     tags->setPrefetcher(prefetcher);
 155     missQueue->setCache(this);
 156     missQueue->setPrefetcher(prefetcher);
 157     coherence->setCache(this);
 158     prefetcher->setCache(this);
 159     prefetcher->setTags(tags);
 160     prefetcher->setBuffer(missQueue);
 161     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 162     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 163 }
 164
 165 template<class TagStore, class Buffering, class Coherence>
 166 void
 167 Cache<TagStore,Buffering,Coherence>::regStats()
 168 {
 169     BaseCache::regStats();
 170     tags->regStats(name());
 171     missQueue->regStats(name());
 172     coherence->regStats(name());
 173     prefetcher->regStats(name());
 174 }
 175
 176 template<class TagStore, class Buffering, class Coherence>
 177 bool
 178 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 179 {
 180 //@todo Add back in MemDebug Calls
 181 //    MemDebug::cacheAccess(pkt);
 182     BlkType *blk = NULL;
 183     PacketList writebacks;
 184     int size = blkSize;
 185     int lat = hitLatency;
 186     if (prefetchAccess) {
 187         //We are determining prefetches on access stream, call prefetcher
 188         prefetcher->handleMiss(pkt, curTick);
 189     }
 190     if (!pkt->req->isUncacheable()) {
 191         blk = tags->handleAccess(pkt, lat, writebacks);
 192     } else {
 193         size = pkt->getSize();
 194     }
 195     // If this is a block size write/hint (WH64) allocate the block here
 196     // if the coherence protocol allows it.
 197     /** @todo make the fast write alloc (wh64) work with coherence. */
 198     /** @todo Do we want to do fast writes for writebacks as well? */
 199     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 200         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 201         // not outstanding misses, can do this
 202         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 203         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 204             if (outstanding_miss) {
 205                 warn("WriteInv doing a fastallocate"
 206                      "with an outstanding miss to the same address\n");
 207             }
 208             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 209                                    writebacks);
 210             ++fastWrites;
 211         }
 212     }
 213     while (!writebacks.empty()) {
 214         missQueue->doWriteback(writebacks.front());
 215         writebacks.pop_front();
 216     }
 217     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 218             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 219             pkt->getAddr() & ~((Addr)blkSize - 1));
 220     if (blk) {
 221         // Hit
 222         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 223         // clear dirty bit if write through
 224         if (pkt->needsResponse())
 225             respond(pkt, curTick+lat);
 226         if (pkt->cmd == Packet::Writeback) {
 227             //Signal that you can kill the pkt/req
 228             pkt->flags |= SATISFIED;
 229         }
 230         return true;
 231     }
 232
 233     // Miss
 234     if (!pkt->req->isUncacheable()) {
 235         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 236         /** @todo Move miss count code into BaseCache */
 237         if (missCount) {
 238             --missCount;
 239             if (missCount == 0)
 240                 exitSimLoop("A cache reached the maximum miss count");
 241         }
 242     }
 243     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 244 //    return MA_CACHE_MISS;
 245     return true;
 246 }
 247
 248
 249 template<class TagStore, class Buffering, class Coherence>
 250 Packet *
 251 Cache<TagStore,Buffering,Coherence>::getPacket()
 252 {
 253     assert(missQueue->havePending());
 254     Packet * pkt = missQueue->getPacket();
 255     if (pkt) {
 256         if (!pkt->req->isUncacheable()) {
 257             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 258             BlkType *blk = tags->findBlock(pkt);
 259             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 260                                               (blk)? blk->status : 0);
 261             missQueue->setBusCmd(pkt, cmd);
 262         }
 263     }
 264
 265     assert(!doMasterRequest() || missQueue->havePending());
 266     assert(!pkt || pkt->time <= curTick);
 267     return pkt;
 268 }
 269
 270 template<class TagStore, class Buffering, class Coherence>
 271 void
 272 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
 273 {
 274     if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
 275         if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)
 276             && (pkt && (pkt->flags & SATISFIED))) {
 277             //Writeback, clean up the non copy version of the packet
 278             delete pkt;
 279         }
 280         missQueue->markInService(mshr->pkt, mshr);
 281         //Temp Hack for UPGRADES
 282         if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) {
 283             assert(pkt);  //Upgrades need to be fixed
 284             pkt->flags &= ~CACHE_LINE_FILL;
 285             BlkType *blk = tags->findBlock(pkt);
 286             CacheBlk::State old_state = (blk) ? blk->status : 0;
 287             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 288             if (old_state != new_state)
 289                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 290                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 291             //Set the state on the upgrade
 292             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 293             PacketList writebacks;
 294             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 295             assert(writebacks.empty());
 296             missQueue->handleResponse(pkt, curTick + hitLatency);
 297         }
 298     } else if (pkt && !pkt->req->isUncacheable()) {
 299         pkt->flags &= ~NACKED_LINE;
 300         pkt->flags &= ~SATISFIED;
 301         pkt->flags &= ~SNOOP_COMMIT;
 302
 303 //Rmove copy from mshr
 304         delete mshr->pkt;
 305         mshr->pkt = pkt;
 306
 307         missQueue->restoreOrigCmd(pkt);
 308     }
 309 }
 310
 311 template<class TagStore, class Buffering, class Coherence>
 312 void
 313 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 314 {
 315     BlkType *blk = NULL;
 316     if (pkt->senderState) {
 317         //Delete temp copy in MSHR, restore it.
 318         delete ((MSHR*)pkt->senderState)->pkt;
 319         ((MSHR*)pkt->senderState)->pkt = pkt;
 320         if (pkt->result == Packet::Nacked) {
 321             //pkt->reinitFromRequest();
 322             warn("NACKs from devices not connected to the same bus not implemented\n");
 323             return;
 324         }
 325         if (pkt->result == Packet::BadAddress) {
 326             //Make the response a Bad address and send it
 327         }
 328 //      MemDebug::cacheResponse(pkt);
 329         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 330                 pkt->getAddr() & (((ULL(1))<<48)-1));
 331
 332         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 333             blk = tags->findBlock(pkt);
 334             CacheBlk::State old_state = (blk) ? blk->status : 0;
 335             PacketList writebacks;
 336             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 337             if (old_state != new_state)
 338                 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 339                         pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 340             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 341                                    new_state, writebacks, pkt);
 342             while (!writebacks.empty()) {
 343                     missQueue->doWriteback(writebacks.front());
 344                     writebacks.pop_front();
 345             }
 346         }
 347         missQueue->handleResponse(pkt, curTick + hitLatency);
 348     }
 349 }
 350
 351 template<class TagStore, class Buffering, class Coherence>
 352 Packet *
 353 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 354 {
 355     return coherence->getPacket();
 356 }
 357
 358 template<class TagStore, class Buffering, class Coherence>
 359 void
 360 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
 361                                                          MSHR *cshr,
 362                                                          bool success)
 363 {
 364     coherence->sendResult(pkt, cshr, success);
 365 }
 366
 367
 368 template<class TagStore, class Buffering, class Coherence>
 369 void
 370 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 371 {
 372     if (pkt->req->isUncacheable()) {
 373         //Can't get a hit on an uncacheable address
 374         //Revisit this for multi level coherence
 375         return;
 376     }
 377     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 378     BlkType *blk = tags->findBlock(pkt);
 379     MSHR *mshr = missQueue->findMSHR(blk_addr);
 380     if (coherence->hasProtocol()) { //@todo Move this into handle bus req
 381         //If we find an mshr, and it is in service, we need to NACK or invalidate
 382         if (mshr) {
 383             if (mshr->inService) {
 384                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 385                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 386                     //If the outstanding request was an invalidate (upgrade,readex,..)
 387                     //Then we need to ACK the request until we get the data
 388                     //Also NACK if the outstanding request is not a cachefill (writeback)
 389                     assert(!(pkt->flags & SATISFIED));
 390                     pkt->flags |= SATISFIED;
 391                     pkt->flags |= NACKED_LINE;
 392                     ///@todo NACK's from other levels
 393                     //warn("NACKs from devices not connected to the same bus not implemented\n");
 394                     //respondToSnoop(pkt, curTick + hitLatency);
 395                     return;
 396                 }
 397                 else {
 398                     //The supplier will be someone else, because we are waiting for
 399                     //the data.  This should cause this cache to be forced to go to
 400                     //the shared state, not the exclusive even though the shared line
 401                     //won't be asserted.  But for now we will just invlidate ourselves
 402                     //and allow the other cache to go into the exclusive state.
 403                     //@todo Make it so a read to a pending read doesn't invalidate.
 404                     //@todo Make it so that a read to a pending read can't be exclusive now.
 405
 406                     //Set the address so find match works
 407                     //panic("Don't have invalidates yet\n");
 408                     invalidatePkt->addrOverride(pkt->getAddr());
 409
 410                     //Append the invalidate on
 411                     missQueue->addTarget(mshr,invalidatePkt);
 412                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 413                     return;
 414                 }
 415             }
 416         }
 417         //We also need to check the writeback buffers and handle those
 418         std::vector<MSHR *> writebacks;
 419         if (missQueue->findWrites(blk_addr, writebacks)) {
 420             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 421
 422             //Look through writebacks for any non-uncachable writes, use that
 423             for (int i=0; i<writebacks.size(); i++) {
 424                 mshr = writebacks[i];
 425
 426                 if (!mshr->pkt->req->isUncacheable()) {
 427                     if (pkt->isRead()) {
 428                         //Only Upgrades don't get here
 429                         //Supply the data
 430                         assert(!(pkt->flags & SATISFIED));
 431                         pkt->flags |= SATISFIED;
 432
 433                         //If we are in an exclusive protocol, make it ask again
 434                         //to get write permissions (upgrade), signal shared
 435                         pkt->flags |= SHARED_LINE;
 436
 437                         assert(pkt->isRead());
 438                         Addr offset = pkt->getAddr() & (blkSize - 1);
 439                         assert(offset < blkSize);
 440                         assert(pkt->getSize() <= blkSize);
 441                         assert(offset + pkt->getSize() <=blkSize);
 442                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 443
 444                         respondToSnoop(pkt, curTick + hitLatency);
 445                     }
 446
 447                     if (pkt->isInvalidate()) {
 448                         //This must be an upgrade or other cache will take ownership
 449                         missQueue->markInService(mshr->pkt, mshr);
 450                     }
 451                     return;
 452                 }
 453             }
 454         }
 455     }
 456     CacheBlk::State new_state;
 457     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 458     if (satisfy) {
 459         DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 460                 "new state is %i\n",
 461                 pkt->cmdString(), blk_addr, new_state);
 462
 463         tags->handleSnoop(blk, new_state, pkt);
 464         respondToSnoop(pkt, curTick + hitLatency);
 465         return;
 466     }
 467     if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 468                      pkt->cmdString(), blk_addr, new_state);
 469     tags->handleSnoop(blk, new_state);
 470 }
 471
 472 template<class TagStore, class Buffering, class Coherence>
 473 void
 474 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 475 {
 476     //Need to handle the response, if NACKED
 477     if (pkt->flags & NACKED_LINE) {
 478         //Need to mark it as not in service, and retry for bus
 479         assert(0); //Yeah, we saw a NACK come through
 480
 481         //For now this should never get called, we return false when we see a NACK
 482         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 483         //For now it retrys in just 2 cycles, need to figure out how to change that
 484         //Eventually we will want to also have success come in as a parameter
 485         //Need to make sure that we handle the functionality that happens on successufl
 486         //return of the sendAddr function
 487     }
 488 }
 489
 490 template<class TagStore, class Buffering, class Coherence>
 491 void
 492 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 493 {
 494     tags->invalidateBlk(addr);
 495 }
 496
 497
 498 /**
 499  * @todo Fix to not assume write allocate
 500  */
 501 template<class TagStore, class Buffering, class Coherence>
 502 Tick
 503 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
 504 {
 505 //    MemDebug::cacheProbe(pkt);
 506     if (!pkt->req->isUncacheable()) {
 507         if (pkt->isInvalidate() && !pkt->isRead()
 508             && !pkt->isWrite()) {
 509             //Upgrade or Invalidate, satisfy it, don't forward
 510             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 511                     pkt->getAddr() & (((ULL(1))<<48)-1),
 512                     pkt->getAddr() & ~((Addr)blkSize - 1));
 513             pkt->flags |= SATISFIED;
 514             return 0;
 515         }
 516     }
 517
 518     PacketList writebacks;
 519     int lat;
 520     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 521
 522     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 523             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 524             pkt->getAddr() & ~((Addr)blkSize - 1));
 525
 526     if (!blk) {
 527         // Need to check for outstanding misses and writes
 528         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 529
 530         // There can only be one matching outstanding miss.
 531         MSHR* mshr = missQueue->findMSHR(blk_addr);
 532
 533         // There can be many matching outstanding writes.
 534         std::vector<MSHR*> writes;
 535         missQueue->findWrites(blk_addr, writes);
 536
 537         if (!update) {
 538                 otherSidePort->sendFunctional(pkt);
 539
 540             // Check for data in MSHR and writebuffer.
 541             if (mshr) {
 542                 warn("Found outstanding miss on an non-update probe");
 543                 MSHR::TargetList *targets = mshr->getTargetList();
 544                 MSHR::TargetList::iterator i = targets->begin();
 545                 MSHR::TargetList::iterator end = targets->end();
 546                 for (; i != end; ++i) {
 547                     Packet * target = *i;
 548                     // If the target contains data, and it overlaps the
 549                     // probed request, need to update data
 550                     if (target->isWrite() && target->intersect(pkt)) {
 551                         uint8_t* pkt_data;
 552                         uint8_t* write_data;
 553                         int data_size;
 554                         if (target->getAddr() < pkt->getAddr()) {
 555                             int offset = pkt->getAddr() - target->getAddr();
 556                             pkt_data = pkt->getPtr<uint8_t>();
 557                             write_data = target->getPtr<uint8_t>() + offset;
 558                             data_size = target->getSize() - offset;
 559                             assert(data_size > 0);
 560                             if (data_size > pkt->getSize())
 561                                 data_size = pkt->getSize();
 562                         } else {
 563                             int offset = target->getAddr() - pkt->getAddr();
 564                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 565                             write_data = target->getPtr<uint8_t>();
 566                             data_size = pkt->getSize() - offset;
 567                             assert(data_size > pkt->getSize());
 568                             if (data_size > target->getSize())
 569                                 data_size = target->getSize();
 570                         }
 571
 572                         if (pkt->isWrite()) {
 573                             memcpy(pkt_data, write_data, data_size);
 574                         } else {
 575                             memcpy(write_data, pkt_data, data_size);
 576                         }
 577                     }
 578                 }
 579             }
 580             for (int i = 0; i < writes.size(); ++i) {
 581                 Packet * write = writes[i]->pkt;
 582                 if (write->intersect(pkt)) {
 583                     warn("Found outstanding write on an non-update probe");
 584                     uint8_t* pkt_data;
 585                     uint8_t* write_data;
 586                     int data_size;
 587                     if (write->getAddr() < pkt->getAddr()) {
 588                         int offset = pkt->getAddr() - write->getAddr();
 589                         pkt_data = pkt->getPtr<uint8_t>();
 590                         write_data = write->getPtr<uint8_t>() + offset;
 591                         data_size = write->getSize() - offset;
 592                         assert(data_size > 0);
 593                         if (data_size > pkt->getSize())
 594                             data_size = pkt->getSize();
 595                     } else {
 596                         int offset = write->getAddr() - pkt->getAddr();
 597                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 598                         write_data = write->getPtr<uint8_t>();
 599                         data_size = pkt->getSize() - offset;
 600                         assert(data_size > pkt->getSize());
 601                         if (data_size > write->getSize())
 602                             data_size = write->getSize();
 603                     }
 604
 605                     if (pkt->isWrite()) {
 606                         memcpy(pkt_data, write_data, data_size);
 607                     } else {
 608                         memcpy(write_data, pkt_data, data_size);
 609                     }
 610
 611                 }
 612             }
 613             return 0;
 614         } else {
 615             // update the cache state and statistics
 616             if (mshr || !writes.empty()){
 617                 // Can't handle it, return pktuest unsatisfied.
 618                 panic("Atomic access ran into outstanding MSHR's or WB's!");
 619             }
 620             if (!pkt->req->isUncacheable()) {
 621                 // Fetch the cache block to fill
 622                 BlkType *blk = tags->findBlock(pkt);
 623                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 624                                                    (blk)? blk->status : 0);
 625
 626                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 627
 628                 busPkt->allocate();
 629
 630                 busPkt->time = curTick;
 631
 632                 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
 633                         busPkt->cmdString(),
 634                         busPkt->getAddr() & (((ULL(1))<<48)-1),
 635                         busPkt->getAddr() & ~((Addr)blkSize - 1));
 636
 637                 lat = memSidePort->sendAtomic(busPkt);
 638
 639                 //Be sure to flip the response to a request for coherence
 640                 if (busPkt->needsResponse()) {
 641                     busPkt->makeAtomicResponse();
 642                 }
 643
 644 /*              if (!(busPkt->flags & SATISFIED)) {
 645                     // blocked at a higher level, just return
 646                     return 0;
 647                 }
 648
 649 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 650
 651                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 652                 CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
 653                     DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
 654                             busPkt->cmdString(),
 655                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
 656                 if (old_state != new_state)
 657                     DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 658                             busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 659
 660                 tags->handleFill(blk, busPkt,
 661                                  new_state,
 662                                  writebacks, pkt);
 663                 //Free the packet
 664                 delete busPkt;
 665
 666                 // Handle writebacks if needed
 667                 while (!writebacks.empty()){
 668                     Packet *wbPkt = writebacks.front();
 669                     memSidePort->sendAtomic(wbPkt);
 670                     writebacks.pop_front();
 671                     delete wbPkt;
 672                 }
 673                 return lat + hitLatency;
 674             } else {
 675                 return memSidePort->sendAtomic(pkt);
 676             }
 677         }
 678     } else {
 679         // There was a cache hit.
 680         // Handle writebacks if needed
 681         while (!writebacks.empty()){
 682             memSidePort->sendAtomic(writebacks.front());
 683             writebacks.pop_front();
 684         }
 685
 686         if (update) {
 687             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 688         } else if (pkt->isWrite()) {
 689             // Still need to change data in all locations.
 690             otherSidePort->sendFunctional(pkt);
 691         }
 692         return hitLatency;
 693     }
 694     fatal("Probe not handled.\n");
 695     return 0;
 696 }
 697
 698 template<class TagStore, class Buffering, class Coherence>
 699 Tick
 700 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 701 {
 702         Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 703         BlkType *blk = tags->findBlock(pkt);
 704         MSHR *mshr = missQueue->findMSHR(blk_addr);
 705         CacheBlk::State new_state = 0;
 706         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 707         if (satisfy) {
 708             DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 709                     "new state is %i\n",
 710                     pkt->cmdString(), blk_addr, new_state);
 711
 712             tags->handleSnoop(blk, new_state, pkt);
 713             return hitLatency;
 714         }
 715         if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 716                      pkt->cmdString(), blk_addr, new_state);
 717         tags->handleSnoop(blk, new_state);
 718         return 0;
 719 }
 720