2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
45 #include "sim/host.hh"
46 #include "base/misc.hh"
49 #include "mem/cache/cache.hh"
50 #include "mem/cache/cache_blk.hh"
51 #include "mem/cache/miss/mshr.hh"
52 #include "mem/cache/prefetch/prefetcher.hh"
54 #include "sim/sim_exit.hh" // for SimExitEvent
56 template<class TagStore, class Buffering, class Coherence>
58 Cache<TagStore,Buffering,Coherence>::
59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
63 if (pkt->isWrite() && (pkt->req->isLocked())) {
64 pkt->req->setScResult(1);
71 if (pkt->isResponse())
74 //Check if we should do the snoop
75 if (pkt->flags & SNOOP_COMMIT)
82 template<class TagStore, class Buffering, class Coherence>
84 Cache<TagStore,Buffering,Coherence>::
85 doAtomicAccess(Packet *pkt, bool isCpuSide)
89 //Temporary solution to LL/SC
90 if (pkt->isWrite() && (pkt->req->isLocked())) {
91 pkt->req->setScResult(1);
94 probe(pkt, true, NULL);
95 //TEMP ALWAYS SUCCES FOR NOW
96 pkt->result = Packet::Success;
100 if (pkt->isResponse())
103 return snoopProbe(pkt);
105 //Fix this timing info
109 template<class TagStore, class Buffering, class Coherence>
111 Cache<TagStore,Buffering,Coherence>::
112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
116 //TEMP USE CPU?THREAD 0 0
117 pkt->req->setThreadContext(0,0);
119 //Temporary solution to LL/SC
120 if (pkt->isWrite() && (pkt->req->isLocked())) {
121 assert("Can't handle LL/SC on functional path\n");
124 probe(pkt, false, memSidePort);
125 //TEMP ALWAYS SUCCESFUL FOR NOW
126 pkt->result = Packet::Success;
130 probe(pkt, false, cpuSidePort);
134 template<class TagStore, class Buffering, class Coherence>
136 Cache<TagStore,Buffering,Coherence>::
137 recvStatusChange(Port::Status status, bool isCpuSide)
143 template<class TagStore, class Buffering, class Coherence>
144 Cache<TagStore,Buffering,Coherence>::
145 Cache(const std::string &_name,
146 Cache<TagStore,Buffering,Coherence>::Params ¶ms)
147 : BaseCache(_name, params.baseParams),
148 prefetchAccess(params.prefetchAccess),
149 tags(params.tags), missQueue(params.missQueue),
150 coherence(params.coherence), prefetcher(params.prefetcher),
151 doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
152 hitLatency(params.hitLatency)
154 tags->setCache(this);
155 tags->setPrefetcher(prefetcher);
156 missQueue->setCache(this);
157 missQueue->setPrefetcher(prefetcher);
158 coherence->setCache(this);
159 prefetcher->setCache(this);
160 prefetcher->setTags(tags);
161 prefetcher->setBuffer(missQueue);
162 invalidateReq = new Request((Addr) NULL, blkSize, 0);
163 invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
166 template<class TagStore, class Buffering, class Coherence>
168 Cache<TagStore,Buffering,Coherence>::regStats()
170 BaseCache::regStats();
171 tags->regStats(name());
172 missQueue->regStats(name());
173 coherence->regStats(name());
174 prefetcher->regStats(name());
177 template<class TagStore, class Buffering, class Coherence>
179 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
181 //@todo Add back in MemDebug Calls
182 // MemDebug::cacheAccess(pkt);
184 PacketList writebacks;
186 int lat = hitLatency;
187 if (prefetchAccess) {
188 //We are determining prefetches on access stream, call prefetcher
189 prefetcher->handleMiss(pkt, curTick);
191 if (!pkt->req->isUncacheable()) {
192 blk = tags->handleAccess(pkt, lat, writebacks);
194 size = pkt->getSize();
196 // If this is a block size write/hint (WH64) allocate the block here
197 // if the coherence protocol allows it.
198 /** @todo make the fast write alloc (wh64) work with coherence. */
199 /** @todo Do we want to do fast writes for writebacks as well? */
200 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
201 (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
202 // not outstanding misses, can do this
203 MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
204 if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
205 if (outstanding_miss) {
206 warn("WriteInv doing a fastallocate"
207 "with an outstanding miss to the same address\n");
209 blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
214 while (!writebacks.empty()) {
215 missQueue->doWriteback(writebacks.front());
216 writebacks.pop_front();
218 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
219 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
220 pkt->getAddr() & ~((Addr)blkSize - 1));
223 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
224 // clear dirty bit if write through
225 if (pkt->needsResponse())
226 respond(pkt, curTick+lat);
227 if (pkt->cmd == Packet::Writeback) {
228 //Signal that you can kill the pkt/req
229 pkt->flags |= SATISFIED;
235 if (!pkt->req->isUncacheable()) {
236 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
237 /** @todo Move miss count code into BaseCache */
241 exitSimLoop("A cache reached the maximum miss count");
244 missQueue->handleMiss(pkt, size, curTick + hitLatency);
245 // return MA_CACHE_MISS;
250 template<class TagStore, class Buffering, class Coherence>
252 Cache<TagStore,Buffering,Coherence>::getPacket()
254 assert(missQueue->havePending());
255 Packet * pkt = missQueue->getPacket();
257 if (!pkt->req->isUncacheable()) {
258 if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
259 BlkType *blk = tags->findBlock(pkt);
260 Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
261 (blk)? blk->status : 0);
262 missQueue->setBusCmd(pkt, cmd);
266 assert(!doMasterRequest() || missQueue->havePending());
267 assert(!pkt || pkt->time <= curTick);
271 template<class TagStore, class Buffering, class Coherence>
273 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
275 if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
276 missQueue->markInService(mshr->pkt, mshr);
277 //Temp Hack for UPGRADES
278 if (mshr->pkt->cmd == Packet::UpgradeReq) {
279 assert(pkt); //Upgrades need to be fixed
280 pkt->flags &= ~CACHE_LINE_FILL;
281 BlkType *blk = tags->findBlock(pkt);
282 CacheBlk::State old_state = (blk) ? blk->status : 0;
283 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
284 if (old_state != new_state)
285 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
286 pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
287 //Set the state on the upgrade
288 memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
289 PacketList writebacks;
290 tags->handleFill(blk, mshr, new_state, writebacks, pkt);
291 assert(writebacks.empty());
292 missQueue->handleResponse(pkt, curTick + hitLatency);
294 } else if (pkt && !pkt->req->isUncacheable()) {
295 pkt->flags &= ~NACKED_LINE;
296 pkt->flags &= ~SATISFIED;
297 pkt->flags &= ~SNOOP_COMMIT;
298 missQueue->restoreOrigCmd(pkt);
302 template<class TagStore, class Buffering, class Coherence>
304 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
307 if (pkt->senderState) {
308 //Delete temp copy in MSHR, restore it.
309 delete ((MSHR*)pkt->senderState)->pkt;
310 ((MSHR*)pkt->senderState)->pkt = pkt;
311 if (pkt->result == Packet::Nacked) {
312 //pkt->reinitFromRequest();
313 warn("NACKs from devices not connected to the same bus not implemented\n");
316 if (pkt->result == Packet::BadAddress) {
317 //Make the response a Bad address and send it
319 // MemDebug::cacheResponse(pkt);
320 DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
321 pkt->getAddr() & (((ULL(1))<<48)-1));
323 if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
324 blk = tags->findBlock(pkt);
325 CacheBlk::State old_state = (blk) ? blk->status : 0;
326 PacketList writebacks;
327 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
328 if (old_state != new_state)
329 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
330 pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
331 blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
332 new_state, writebacks, pkt);
333 while (!writebacks.empty()) {
334 missQueue->doWriteback(writebacks.front());
335 writebacks.pop_front();
338 missQueue->handleResponse(pkt, curTick + hitLatency);
342 template<class TagStore, class Buffering, class Coherence>
344 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
346 // Need to temporarily move this blk into MSHRs
347 MSHR *mshr = missQueue->allocateTargetList(addr);
350 // Read the data into the mshr
351 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
352 assert(dummy.empty());
353 assert(mshr->pkt->flags & SATISFIED);
354 // can overload order since it isn't used on non pending blocks
355 mshr->order = blk->status;
356 // temporarily remove the block from the cache.
357 tags->invalidateBlk(addr);
360 template<class TagStore, class Buffering, class Coherence>
362 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
364 // Need to temporarily move this blk into MSHRs
365 assert(mshr->pkt->cmd == Packet::ReadReq);
368 // Read the data into the mshr
369 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
370 assert(dummy.empty());
371 assert(mshr->pkt->flags & SATISFIED);
372 // can overload order since it isn't used on non pending blocks
373 mshr->order = blk->status;
374 // temporarily remove the block from the cache.
375 tags->invalidateBlk(mshr->pkt->getAddr());
379 template<class TagStore, class Buffering, class Coherence>
381 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
383 return coherence->getPacket();
386 template<class TagStore, class Buffering, class Coherence>
388 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
392 coherence->sendResult(pkt, cshr, success);
396 template<class TagStore, class Buffering, class Coherence>
398 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
400 if (pkt->req->isUncacheable()) {
401 //Can't get a hit on an uncacheable address
402 //Revisit this for multi level coherence
405 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
406 BlkType *blk = tags->findBlock(pkt);
407 MSHR *mshr = missQueue->findMSHR(blk_addr);
408 if (coherence->hasProtocol()) { //@todo Move this into handle bus req
409 //If we find an mshr, and it is in service, we need to NACK or invalidate
411 if (mshr->inService) {
412 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
413 && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
414 //If the outstanding request was an invalidate (upgrade,readex,..)
415 //Then we need to ACK the request until we get the data
416 //Also NACK if the outstanding request is not a cachefill (writeback)
417 assert(!(pkt->flags & SATISFIED));
418 pkt->flags |= SATISFIED;
419 pkt->flags |= NACKED_LINE;
420 ///@todo NACK's from other levels
421 //warn("NACKs from devices not connected to the same bus not implemented\n");
422 //respondToSnoop(pkt, curTick + hitLatency);
426 //The supplier will be someone else, because we are waiting for
427 //the data. This should cause this cache to be forced to go to
428 //the shared state, not the exclusive even though the shared line
429 //won't be asserted. But for now we will just invlidate ourselves
430 //and allow the other cache to go into the exclusive state.
431 //@todo Make it so a read to a pending read doesn't invalidate.
432 //@todo Make it so that a read to a pending read can't be exclusive now.
434 //Set the address so find match works
435 //panic("Don't have invalidates yet\n");
436 invalidatePkt->addrOverride(pkt->getAddr());
438 //Append the invalidate on
439 missQueue->addTarget(mshr,invalidatePkt);
440 DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
445 //We also need to check the writeback buffers and handle those
446 std::vector<MSHR *> writebacks;
447 if (missQueue->findWrites(blk_addr, writebacks)) {
448 DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
450 //Look through writebacks for any non-uncachable writes, use that
451 for (int i=0; i<writebacks.size(); i++) {
452 mshr = writebacks[i];
454 if (!mshr->pkt->req->isUncacheable()) {
456 //Only Upgrades don't get here
458 assert(!(pkt->flags & SATISFIED));
459 pkt->flags |= SATISFIED;
461 //If we are in an exclusive protocol, make it ask again
462 //to get write permissions (upgrade), signal shared
463 pkt->flags |= SHARED_LINE;
465 assert(pkt->isRead());
466 Addr offset = pkt->getAddr() & (blkSize - 1);
467 assert(offset < blkSize);
468 assert(pkt->getSize() <= blkSize);
469 assert(offset + pkt->getSize() <=blkSize);
470 memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
472 respondToSnoop(pkt, curTick + hitLatency);
475 if (pkt->isInvalidate()) {
476 //This must be an upgrade or other cache will take ownership
477 missQueue->markInService(mshr->pkt, mshr);
484 CacheBlk::State new_state;
485 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
487 DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
489 pkt->cmdString(), blk_addr, new_state);
491 tags->handleSnoop(blk, new_state, pkt);
492 respondToSnoop(pkt, curTick + hitLatency);
495 if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
496 pkt->cmdString(), blk_addr, new_state);
497 tags->handleSnoop(blk, new_state);
500 template<class TagStore, class Buffering, class Coherence>
502 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
504 //Need to handle the response, if NACKED
505 if (pkt->flags & NACKED_LINE) {
506 //Need to mark it as not in service, and retry for bus
507 assert(0); //Yeah, we saw a NACK come through
509 //For now this should never get called, we return false when we see a NACK
510 //instead, by doing this we allow the bus_blocked mechanism to handle the retry
511 //For now it retrys in just 2 cycles, need to figure out how to change that
512 //Eventually we will want to also have success come in as a parameter
513 //Need to make sure that we handle the functionality that happens on successufl
514 //return of the sendAddr function
518 template<class TagStore, class Buffering, class Coherence>
520 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
522 tags->invalidateBlk(addr);
527 * @todo Fix to not assume write allocate
529 template<class TagStore, class Buffering, class Coherence>
531 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
533 // MemDebug::cacheProbe(pkt);
534 if (!pkt->req->isUncacheable()) {
535 if (pkt->isInvalidate() && !pkt->isRead()
536 && !pkt->isWrite()) {
537 //Upgrade or Invalidate, satisfy it, don't forward
538 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
539 pkt->getAddr() & (((ULL(1))<<48)-1),
540 pkt->getAddr() & ~((Addr)blkSize - 1));
541 pkt->flags |= SATISFIED;
546 PacketList writebacks;
548 BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
550 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
551 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
552 pkt->getAddr() & ~((Addr)blkSize - 1));
555 // Need to check for outstanding misses and writes
556 Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
558 // There can only be one matching outstanding miss.
559 MSHR* mshr = missQueue->findMSHR(blk_addr);
561 // There can be many matching outstanding writes.
562 std::vector<MSHR*> writes;
563 missQueue->findWrites(blk_addr, writes);
566 otherSidePort->sendFunctional(pkt);
568 // Check for data in MSHR and writebuffer.
570 warn("Found outstanding miss on an non-update probe");
571 MSHR::TargetList *targets = mshr->getTargetList();
572 MSHR::TargetList::iterator i = targets->begin();
573 MSHR::TargetList::iterator end = targets->end();
574 for (; i != end; ++i) {
575 Packet * target = *i;
576 // If the target contains data, and it overlaps the
577 // probed request, need to update data
578 if (target->isWrite() && target->intersect(pkt)) {
582 if (target->getAddr() < pkt->getAddr()) {
583 int offset = pkt->getAddr() - target->getAddr();
584 pkt_data = pkt->getPtr<uint8_t>();
585 write_data = target->getPtr<uint8_t>() + offset;
586 data_size = target->getSize() - offset;
587 assert(data_size > 0);
588 if (data_size > pkt->getSize())
589 data_size = pkt->getSize();
591 int offset = target->getAddr() - pkt->getAddr();
592 pkt_data = pkt->getPtr<uint8_t>() + offset;
593 write_data = target->getPtr<uint8_t>();
594 data_size = pkt->getSize() - offset;
595 assert(data_size > pkt->getSize());
596 if (data_size > target->getSize())
597 data_size = target->getSize();
600 if (pkt->isWrite()) {
601 memcpy(pkt_data, write_data, data_size);
603 memcpy(write_data, pkt_data, data_size);
608 for (int i = 0; i < writes.size(); ++i) {
609 Packet * write = writes[i]->pkt;
610 if (write->intersect(pkt)) {
611 warn("Found outstanding write on an non-update probe");
615 if (write->getAddr() < pkt->getAddr()) {
616 int offset = pkt->getAddr() - write->getAddr();
617 pkt_data = pkt->getPtr<uint8_t>();
618 write_data = write->getPtr<uint8_t>() + offset;
619 data_size = write->getSize() - offset;
620 assert(data_size > 0);
621 if (data_size > pkt->getSize())
622 data_size = pkt->getSize();
624 int offset = write->getAddr() - pkt->getAddr();
625 pkt_data = pkt->getPtr<uint8_t>() + offset;
626 write_data = write->getPtr<uint8_t>();
627 data_size = pkt->getSize() - offset;
628 assert(data_size > pkt->getSize());
629 if (data_size > write->getSize())
630 data_size = write->getSize();
633 if (pkt->isWrite()) {
634 memcpy(pkt_data, write_data, data_size);
636 memcpy(write_data, pkt_data, data_size);
643 // update the cache state and statistics
644 if (mshr || !writes.empty()){
645 // Can't handle it, return pktuest unsatisfied.
646 panic("Atomic access ran into outstanding MSHR's or WB's!");
648 if (!pkt->req->isUncacheable()) {
649 // Fetch the cache block to fill
650 BlkType *blk = tags->findBlock(pkt);
651 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
652 (blk)? blk->status : 0);
654 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
658 busPkt->time = curTick;
660 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
662 busPkt->getAddr() & (((ULL(1))<<48)-1),
663 busPkt->getAddr() & ~((Addr)blkSize - 1));
665 lat = memSidePort->sendAtomic(busPkt);
667 //Be sure to flip the response to a request for coherence
668 if (busPkt->needsResponse()) {
669 busPkt->makeAtomicResponse();
672 /* if (!(busPkt->flags & SATISFIED)) {
673 // blocked at a higher level, just return
677 */ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
679 CacheBlk::State old_state = (blk) ? blk->status : 0;
680 CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
681 DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
683 busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
684 if (old_state != new_state)
685 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
686 busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
688 tags->handleFill(blk, busPkt,
694 // Handle writebacks if needed
695 while (!writebacks.empty()){
696 Packet *wbPkt = writebacks.front();
697 memSidePort->sendAtomic(wbPkt);
698 writebacks.pop_front();
701 return lat + hitLatency;
703 return memSidePort->sendAtomic(pkt);
707 // There was a cache hit.
708 // Handle writebacks if needed
709 while (!writebacks.empty()){
710 memSidePort->sendAtomic(writebacks.front());
711 writebacks.pop_front();
715 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
716 } else if (pkt->isWrite()) {
717 // Still need to change data in all locations.
718 otherSidePort->sendFunctional(pkt);
722 fatal("Probe not handled.\n");
726 template<class TagStore, class Buffering, class Coherence>
728 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
730 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
731 BlkType *blk = tags->findBlock(pkt);
732 MSHR *mshr = missQueue->findMSHR(blk_addr);
733 CacheBlk::State new_state = 0;
734 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
736 DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
738 pkt->cmdString(), blk_addr, new_state);
740 tags->handleSnoop(blk, new_state, pkt);
743 if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
744 pkt->cmdString(), blk_addr, new_state);
745 tags->handleSnoop(blk, new_state);