src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(PacketPtr pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         probe(pkt, true, NULL);
  90         //TEMP ALWAYS SUCCES FOR NOW
  91         pkt->result = Packet::Success;
  92     }
  93     else
  94     {
  95         if (pkt->isResponse())
  96             handleResponse(pkt);
  97         else
  98             return snoopProbe(pkt);
  99     }
 100     //Fix this timing info
 101     return hitLatency;
 102 }
 103
 104 template<class TagStore, class Buffering, class Coherence>
 105 void
 106 Cache<TagStore,Buffering,Coherence>::
 107 doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
 108 {
 109     if (isCpuSide)
 110     {
 111         //TEMP USE CPU?THREAD 0 0
 112         pkt->req->setThreadContext(0,0);
 113
 114         probe(pkt, false, memSidePort);
 115         //TEMP ALWAYS SUCCESFUL FOR NOW
 116         pkt->result = Packet::Success;
 117     }
 118     else
 119     {
 120             probe(pkt, false, cpuSidePort);
 121     }
 122 }
 123
 124 template<class TagStore, class Buffering, class Coherence>
 125 void
 126 Cache<TagStore,Buffering,Coherence>::
 127 recvStatusChange(Port::Status status, bool isCpuSide)
 128 {
 129
 130 }
 131
 132
 133 template<class TagStore, class Buffering, class Coherence>
 134 Cache<TagStore,Buffering,Coherence>::
 135 Cache(const std::string &_name,
 136       Cache<TagStore,Buffering,Coherence>::Params &params)
 137     : BaseCache(_name, params.baseParams),
 138       prefetchAccess(params.prefetchAccess),
 139       tags(params.tags), missQueue(params.missQueue),
 140       coherence(params.coherence), prefetcher(params.prefetcher),
 141       hitLatency(params.hitLatency)
 142 {
 143     tags->setCache(this);
 144     tags->setPrefetcher(prefetcher);
 145     missQueue->setCache(this);
 146     missQueue->setPrefetcher(prefetcher);
 147     coherence->setCache(this);
 148     prefetcher->setCache(this);
 149     prefetcher->setTags(tags);
 150     prefetcher->setBuffer(missQueue);
 151     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 152     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 153 }
 154
 155 template<class TagStore, class Buffering, class Coherence>
 156 void
 157 Cache<TagStore,Buffering,Coherence>::regStats()
 158 {
 159     BaseCache::regStats();
 160     tags->regStats(name());
 161     missQueue->regStats(name());
 162     coherence->regStats(name());
 163     prefetcher->regStats(name());
 164 }
 165
 166 template<class TagStore, class Buffering, class Coherence>
 167 bool
 168 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 169 {
 170 //@todo Add back in MemDebug Calls
 171 //    MemDebug::cacheAccess(pkt);
 172     BlkType *blk = NULL;
 173     PacketList writebacks;
 174     int size = blkSize;
 175     int lat = hitLatency;
 176     if (prefetchAccess) {
 177         //We are determining prefetches on access stream, call prefetcher
 178         prefetcher->handleMiss(pkt, curTick);
 179     }
 180     if (!pkt->req->isUncacheable()) {
 181         blk = tags->handleAccess(pkt, lat, writebacks);
 182     } else {
 183         size = pkt->getSize();
 184     }
 185     // If this is a block size write/hint (WH64) allocate the block here
 186     // if the coherence protocol allows it.
 187     /** @todo make the fast write alloc (wh64) work with coherence. */
 188     /** @todo Do we want to do fast writes for writebacks as well? */
 189     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 190         (pkt->cmd == Packet::WriteReq
 191          || pkt->cmd == Packet::WriteInvalidateReq) ) {
 192         // not outstanding misses, can do this
 193         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 194         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 195             if (outstanding_miss) {
 196                 warn("WriteInv doing a fastallocate"
 197                      "with an outstanding miss to the same address\n");
 198             }
 199             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 200                                    writebacks);
 201             ++fastWrites;
 202         }
 203     }
 204     while (!writebacks.empty()) {
 205         missQueue->doWriteback(writebacks.front());
 206         writebacks.pop_front();
 207     }
 208     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 209             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 210             pkt->getAddr() & ~((Addr)blkSize - 1));
 211     if (blk) {
 212         // Hit
 213         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 214         // clear dirty bit if write through
 215         if (pkt->needsResponse())
 216             respond(pkt, curTick+lat);
 217         if (pkt->cmd == Packet::Writeback) {
 218             //Signal that you can kill the pkt/req
 219             pkt->flags |= SATISFIED;
 220         }
 221         return true;
 222     }
 223
 224     // Miss
 225     if (!pkt->req->isUncacheable()) {
 226         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 227         /** @todo Move miss count code into BaseCache */
 228         if (missCount) {
 229             --missCount;
 230             if (missCount == 0)
 231                 exitSimLoop("A cache reached the maximum miss count");
 232         }
 233     }
 234
 235     if (pkt->flags & SATISFIED) {
 236         // happens when a store conditional fails because it missed
 237         // the cache completely
 238         if (pkt->needsResponse())
 239             respond(pkt, curTick+lat);
 240     } else {
 241         missQueue->handleMiss(pkt, size, curTick + hitLatency);
 242     }
 243
 244     return true;
 245 }
 246
 247
 248 template<class TagStore, class Buffering, class Coherence>
 249 PacketPtr
 250 Cache<TagStore,Buffering,Coherence>::getPacket()
 251 {
 252     assert(missQueue->havePending());
 253     PacketPtr pkt = missQueue->getPacket();
 254     if (pkt) {
 255         if (!pkt->req->isUncacheable()) {
 256             if (pkt->cmd == Packet::HardPFReq)
 257                 misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 258             BlkType *blk = tags->findBlock(pkt);
 259             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 260                                               (blk)? blk->status : 0);
 261             missQueue->setBusCmd(pkt, cmd);
 262         }
 263     }
 264
 265     assert(!doMasterRequest() || missQueue->havePending());
 266     assert(!pkt || pkt->time <= curTick);
 267     return pkt;
 268 }
 269
 270 template<class TagStore, class Buffering, class Coherence>
 271 void
 272 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
 273                                                 bool success)
 274 {
 275     if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
 276         if (!mshr->pkt->needsResponse()
 277             && !(mshr->pkt->cmd == Packet::UpgradeReq)
 278             && (pkt && (pkt->flags & SATISFIED))) {
 279             //Writeback, clean up the non copy version of the packet
 280             delete pkt;
 281         }
 282         missQueue->markInService(mshr->pkt, mshr);
 283         //Temp Hack for UPGRADES
 284         if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) {
 285             assert(pkt);  //Upgrades need to be fixed
 286             pkt->flags &= ~CACHE_LINE_FILL;
 287             BlkType *blk = tags->findBlock(pkt);
 288             CacheBlk::State old_state = (blk) ? blk->status : 0;
 289             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 290             if (old_state != new_state)
 291                 DPRINTF(Cache, "Block for blk addr %x moving from "
 292                         "state %i to %i\n",
 293                         pkt->getAddr() & (((ULL(1))<<48)-1),
 294                         old_state, new_state);
 295             //Set the state on the upgrade
 296             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 297             PacketList writebacks;
 298             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 299             assert(writebacks.empty());
 300             missQueue->handleResponse(pkt, curTick + hitLatency);
 301         }
 302     } else if (pkt && !pkt->req->isUncacheable()) {
 303         pkt->flags &= ~NACKED_LINE;
 304         pkt->flags &= ~SATISFIED;
 305         pkt->flags &= ~SNOOP_COMMIT;
 306
 307 //Rmove copy from mshr
 308         delete mshr->pkt;
 309         mshr->pkt = pkt;
 310
 311         missQueue->restoreOrigCmd(pkt);
 312     }
 313 }
 314
 315 template<class TagStore, class Buffering, class Coherence>
 316 void
 317 Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
 318 {
 319     BlkType *blk = NULL;
 320     if (pkt->senderState) {
 321         //Delete temp copy in MSHR, restore it.
 322         delete ((MSHR*)pkt->senderState)->pkt;
 323         ((MSHR*)pkt->senderState)->pkt = pkt;
 324         if (pkt->result == Packet::Nacked) {
 325             //pkt->reinitFromRequest();
 326             warn("NACKs from devices not connected to the same bus "
 327                  "not implemented\n");
 328             return;
 329         }
 330         if (pkt->result == Packet::BadAddress) {
 331             //Make the response a Bad address and send it
 332         }
 333 //      MemDebug::cacheResponse(pkt);
 334         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 335                 pkt->getAddr() & (((ULL(1))<<48)-1));
 336
 337         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 338             blk = tags->findBlock(pkt);
 339             CacheBlk::State old_state = (blk) ? blk->status : 0;
 340             PacketList writebacks;
 341             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 342             if (old_state != new_state)
 343                 DPRINTF(Cache, "Block for blk addr %x moving from "
 344                         "state %i to %i\n",
 345                         pkt->getAddr() & (((ULL(1))<<48)-1),
 346                         old_state, new_state);
 347             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 348                                    new_state, writebacks, pkt);
 349             while (!writebacks.empty()) {
 350                     missQueue->doWriteback(writebacks.front());
 351                     writebacks.pop_front();
 352             }
 353         }
 354         missQueue->handleResponse(pkt, curTick + hitLatency);
 355     }
 356 }
 357
 358 template<class TagStore, class Buffering, class Coherence>
 359 PacketPtr
 360 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 361 {
 362     return coherence->getPacket();
 363 }
 364
 365 template<class TagStore, class Buffering, class Coherence>
 366 void
 367 Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
 368                                                          MSHR *cshr,
 369                                                          bool success)
 370 {
 371     coherence->sendResult(pkt, cshr, success);
 372 }
 373
 374
 375 template<class TagStore, class Buffering, class Coherence>
 376 void
 377 Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
 378 {
 379     if (pkt->req->isUncacheable()) {
 380         //Can't get a hit on an uncacheable address
 381         //Revisit this for multi level coherence
 382         return;
 383     }
 384
 385     //Send a timing (true) invalidate up if the protocol calls for it
 386     coherence->propogateInvalidate(pkt, true);
 387
 388     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 389     BlkType *blk = tags->findBlock(pkt);
 390     MSHR *mshr = missQueue->findMSHR(blk_addr);
 391     if (coherence->hasProtocol() || pkt->isInvalidate()) {
 392         //@todo Move this into handle bus req
 393         //If we find an mshr, and it is in service, we need to NACK or
 394         //invalidate
 395         if (mshr) {
 396             if (mshr->inService) {
 397                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 398                     && (pkt->cmd != Packet::InvalidateReq
 399                         && pkt->cmd != Packet::WriteInvalidateReq)) {
 400                     //If the outstanding request was an invalidate
 401                     //(upgrade,readex,..)  Then we need to ACK the request
 402                     //until we get the data Also NACK if the outstanding
 403                     //request is not a cachefill (writeback)
 404                     assert(!(pkt->flags & SATISFIED));
 405                     pkt->flags |= SATISFIED;
 406                     pkt->flags |= NACKED_LINE;
 407                     ///@todo NACK's from other levels
 408                     //warn("NACKs from devices not connected to the same bus "
 409                     //"not implemented\n");
 410                     //respondToSnoop(pkt, curTick + hitLatency);
 411                     return;
 412                 }
 413                 else {
 414                     //The supplier will be someone else, because we are
 415                     //waiting for the data.  This should cause this cache to
 416                     //be forced to go to the shared state, not the exclusive
 417                     //even though the shared line won't be asserted.  But for
 418                     //now we will just invlidate ourselves and allow the other
 419                     //cache to go into the exclusive state.  @todo Make it so
 420                     //a read to a pending read doesn't invalidate.  @todo Make
 421                     //it so that a read to a pending read can't be exclusive
 422                     //now.
 423
 424                     //Set the address so find match works
 425                     //panic("Don't have invalidates yet\n");
 426                     invalidatePkt->addrOverride(pkt->getAddr());
 427
 428                     //Append the invalidate on
 429                     missQueue->addTarget(mshr,invalidatePkt);
 430                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n",
 431                             pkt->getAddr() & (((ULL(1))<<48)-1));
 432                     return;
 433                 }
 434             }
 435         }
 436         //We also need to check the writeback buffers and handle those
 437         std::vector<MSHR *> writebacks;
 438         if (missQueue->findWrites(blk_addr, writebacks)) {
 439             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n",
 440                     pkt->getAddr() & (((ULL(1))<<48)-1));
 441
 442             //Look through writebacks for any non-uncachable writes, use that
 443             for (int i=0; i<writebacks.size(); i++) {
 444                 mshr = writebacks[i];
 445
 446                 if (!mshr->pkt->req->isUncacheable()) {
 447                     if (pkt->isRead()) {
 448                         //Only Upgrades don't get here
 449                         //Supply the data
 450                         assert(!(pkt->flags & SATISFIED));
 451                         pkt->flags |= SATISFIED;
 452
 453                         //If we are in an exclusive protocol, make it ask again
 454                         //to get write permissions (upgrade), signal shared
 455                         pkt->flags |= SHARED_LINE;
 456
 457                         assert(pkt->isRead());
 458                         Addr offset = pkt->getAddr() & (blkSize - 1);
 459                         assert(offset < blkSize);
 460                         assert(pkt->getSize() <= blkSize);
 461                         assert(offset + pkt->getSize() <=blkSize);
 462                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 463
 464                         respondToSnoop(pkt, curTick + hitLatency);
 465                     }
 466
 467                     if (pkt->isInvalidate()) {
 468                         //This must be an upgrade or other cache will take
 469                         //ownership
 470                         missQueue->markInService(mshr->pkt, mshr);
 471                     }
 472                     return;
 473                 }
 474             }
 475         }
 476     }
 477     CacheBlk::State new_state;
 478     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 479     if (satisfy) {
 480         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 481                 "now supplying data, new state is %i\n",
 482                 pkt->cmdString(), blk_addr, new_state);
 483
 484         tags->handleSnoop(blk, new_state, pkt);
 485         respondToSnoop(pkt, curTick + hitLatency);
 486         return;
 487     }
 488     if (blk)
 489         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 490                 "new state is %i\n", pkt->cmdString(), blk_addr, new_state);
 491     tags->handleSnoop(blk, new_state);
 492 }
 493
 494 template<class TagStore, class Buffering, class Coherence>
 495 void
 496 Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
 497 {
 498     //Need to handle the response, if NACKED
 499     if (pkt->flags & NACKED_LINE) {
 500         //Need to mark it as not in service, and retry for bus
 501         assert(0); //Yeah, we saw a NACK come through
 502
 503         //For now this should never get called, we return false when we see a
 504         //NACK instead, by doing this we allow the bus_blocked mechanism to
 505         //handle the retry For now it retrys in just 2 cycles, need to figure
 506         //out how to change that Eventually we will want to also have success
 507         //come in as a parameter Need to make sure that we handle the
 508         //functionality that happens on successufl return of the sendAddr
 509         //function
 510     }
 511 }
 512
 513 template<class TagStore, class Buffering, class Coherence>
 514 void
 515 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 516 {
 517     tags->invalidateBlk(addr);
 518 }
 519
 520
 521 /**
 522  * @todo Fix to not assume write allocate
 523  */
 524 template<class TagStore, class Buffering, class Coherence>
 525 Tick
 526 Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
 527                                            CachePort* otherSidePort)
 528 {
 529 //    MemDebug::cacheProbe(pkt);
 530     if (!pkt->req->isUncacheable()) {
 531         if (pkt->isInvalidate() && !pkt->isRead()
 532             && !pkt->isWrite()) {
 533             //Upgrade or Invalidate, satisfy it, don't forward
 534             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 535                     pkt->getAddr() & (((ULL(1))<<48)-1),
 536                     pkt->getAddr() & ~((Addr)blkSize - 1));
 537             pkt->flags |= SATISFIED;
 538             return 0;
 539         }
 540     }
 541
 542     if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) {
 543         // Still need to change data in all locations.
 544         otherSidePort->sendFunctional(pkt);
 545         if (pkt->isRead() && pkt->result == Packet::Success)
 546             return 0;
 547     }
 548
 549     PacketList writebacks;
 550     int lat;
 551     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 552
 553     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 554             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 555             pkt->getAddr() & ~((Addr)blkSize - 1));
 556
 557
 558     // Need to check for outstanding misses and writes
 559     Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 560
 561     // There can only be one matching outstanding miss.
 562     MSHR* mshr = missQueue->findMSHR(blk_addr);
 563
 564     // There can be many matching outstanding writes.
 565     std::vector<MSHR*> writes;
 566     missQueue->findWrites(blk_addr, writes);
 567
 568     if (!update) {
 569         // Check for data in MSHR and writebuffer.
 570         if (mshr) {
 571             MSHR::TargetList *targets = mshr->getTargetList();
 572             MSHR::TargetList::iterator i = targets->begin();
 573             MSHR::TargetList::iterator end = targets->end();
 574             for (; i != end; ++i) {
 575                 PacketPtr target = *i;
 576                 // If the target contains data, and it overlaps the
 577                 // probed request, need to update data
 578                 if (target->intersect(pkt)) {
 579                     fixPacket(pkt, target);
 580                 }
 581             }
 582         }
 583         for (int i = 0; i < writes.size(); ++i) {
 584             PacketPtr write = writes[i]->pkt;
 585             if (write->intersect(pkt)) {
 586                 fixPacket(pkt, write);
 587             }
 588         }
 589         if (pkt->isRead()
 590             && pkt->result != Packet::Success
 591             && otherSidePort == memSidePort) {
 592             otherSidePort->sendFunctional(pkt);
 593             assert(pkt->result == Packet::Success);
 594         }
 595         return 0;
 596     } else if (!blk && !(pkt->flags & SATISFIED)) {
 597         // update the cache state and statistics
 598         if (mshr || !writes.empty()){
 599             // Can't handle it, return pktuest unsatisfied.
 600             panic("Atomic access ran into outstanding MSHR's or WB's!");
 601         }
 602         if (!pkt->req->isUncacheable()) {
 603                 // Fetch the cache block to fill
 604             BlkType *blk = tags->findBlock(pkt);
 605             Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 606                                                             (blk)? blk->status : 0);
 607
 608             PacketPtr busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 609
 610             busPkt->allocate();
 611
 612             busPkt->time = curTick;
 613
 614             DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
 615                     busPkt->cmdString(),
 616                     busPkt->getAddr() & (((ULL(1))<<48)-1),
 617                     busPkt->getAddr() & ~((Addr)blkSize - 1));
 618
 619             lat = memSidePort->sendAtomic(busPkt);
 620
 621             //Be sure to flip the response to a request for coherence
 622             if (busPkt->needsResponse()) {
 623                 busPkt->makeAtomicResponse();
 624             }
 625
 626 /*              if (!(busPkt->flags & SATISFIED)) {
 627 // blocked at a higher level, just return
 628 return 0;
 629 }
 630
 631 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 632
 633             CacheBlk::State old_state = (blk) ? blk->status : 0;
 634             CacheBlk::State new_state =
 635                 coherence->getNewState(busPkt, old_state);
 636             DPRINTF(Cache,
 637                         "Receive response:%s for blk addr %x in state %i\n",
 638                     busPkt->cmdString(),
 639                     busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
 640             if (old_state != new_state)
 641                     DPRINTF(Cache, "Block for blk addr %x moving from "
 642                             "state %i to %i\n",
 643                             busPkt->getAddr() & (((ULL(1))<<48)-1),
 644                             old_state, new_state);
 645
 646             tags->handleFill(blk, busPkt,
 647                              new_state,
 648                              writebacks, pkt);
 649             //Free the packet
 650             delete busPkt;
 651
 652             // Handle writebacks if needed
 653             while (!writebacks.empty()){
 654                 PacketPtr wbPkt = writebacks.front();
 655                 memSidePort->sendAtomic(wbPkt);
 656                 writebacks.pop_front();
 657                 delete wbPkt;
 658             }
 659                 return lat + hitLatency;
 660         } else {
 661             return memSidePort->sendAtomic(pkt);
 662         }
 663     } else {
 664         if (blk) {
 665             // There was a cache hit.
 666             // Handle writebacks if needed
 667             while (!writebacks.empty()){
 668                 memSidePort->sendAtomic(writebacks.front());
 669                 writebacks.pop_front();
 670             }
 671
 672             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 673         }
 674
 675         return hitLatency;
 676     }
 677
 678     return 0;
 679 }
 680
 681 template<class TagStore, class Buffering, class Coherence>
 682 Tick
 683 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 684 {
 685     //Send a atomic (false) invalidate up if the protocol calls for it
 686     coherence->propogateInvalidate(pkt, false);
 687
 688     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 689     BlkType *blk = tags->findBlock(pkt);
 690     MSHR *mshr = missQueue->findMSHR(blk_addr);
 691     CacheBlk::State new_state = 0;
 692     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 693     if (satisfy) {
 694         DPRINTF(Cache, "Cache snooped a %s request for addr %x and "
 695                 "now supplying data, new state is %i\n",
 696                 pkt->cmdString(), blk_addr, new_state);
 697
 698             tags->handleSnoop(blk, new_state, pkt);
 699             return hitLatency;
 700     }
 701     if (blk)
 702         DPRINTF(Cache, "Cache snooped a %s request for addr %x, "
 703                 "new state is %i\n",
 704                     pkt->cmdString(), blk_addr, new_state);
 705     tags->handleSnoop(blk, new_state);
 706     return 0;
 707 }
 708