2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
45 #include "sim/host.hh"
46 #include "base/misc.hh"
49 #include "mem/cache/cache.hh"
50 #include "mem/cache/cache_blk.hh"
51 #include "mem/cache/miss/mshr.hh"
52 #include "mem/cache/prefetch/prefetcher.hh"
54 #include "sim/sim_exit.hh" // for SimExitEvent
56 template<class TagStore, class Buffering, class Coherence>
58 Cache<TagStore,Buffering,Coherence>::
59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
63 if (pkt->isWrite() && (pkt->req->isLocked())) {
64 pkt->req->setScResult(1);
71 if (pkt->isResponse())
74 //Check if we should do the snoop
75 if (pkt->flags & SNOOP_COMMIT)
82 template<class TagStore, class Buffering, class Coherence>
84 Cache<TagStore,Buffering,Coherence>::
85 doAtomicAccess(Packet *pkt, bool isCpuSide)
89 //Temporary solution to LL/SC
90 if (pkt->isWrite() && (pkt->req->isLocked())) {
91 pkt->req->setScResult(1);
94 probe(pkt, true, NULL);
95 //TEMP ALWAYS SUCCES FOR NOW
96 pkt->result = Packet::Success;
100 if (pkt->isResponse())
103 return snoopProbe(pkt);
105 //Fix this timing info
109 template<class TagStore, class Buffering, class Coherence>
111 Cache<TagStore,Buffering,Coherence>::
112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
116 //TEMP USE CPU?THREAD 0 0
117 pkt->req->setThreadContext(0,0);
119 //Temporary solution to LL/SC
120 if (pkt->isWrite() && (pkt->req->isLocked())) {
121 assert("Can't handle LL/SC on functional path\n");
124 probe(pkt, false, memSidePort);
125 //TEMP ALWAYS SUCCESFUL FOR NOW
126 pkt->result = Packet::Success;
130 probe(pkt, false, cpuSidePort);
134 template<class TagStore, class Buffering, class Coherence>
136 Cache<TagStore,Buffering,Coherence>::
137 recvStatusChange(Port::Status status, bool isCpuSide)
143 template<class TagStore, class Buffering, class Coherence>
144 Cache<TagStore,Buffering,Coherence>::
145 Cache(const std::string &_name,
146 Cache<TagStore,Buffering,Coherence>::Params ¶ms)
147 : BaseCache(_name, params.baseParams),
148 prefetchAccess(params.prefetchAccess),
149 tags(params.tags), missQueue(params.missQueue),
150 coherence(params.coherence), prefetcher(params.prefetcher),
151 doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
152 hitLatency(params.hitLatency)
155 // if (params.in == NULL) {
156 topLevelCache = true;
158 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
159 tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
160 tags->setPrefetcher(prefetcher);
161 missQueue->setCache(this);
162 missQueue->setPrefetcher(prefetcher);
163 coherence->setCache(this);
164 prefetcher->setCache(this);
165 prefetcher->setTags(tags);
166 prefetcher->setBuffer(missQueue);
167 invalidateReq = new Request((Addr) NULL, blkSize, 0);
168 invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
171 template<class TagStore, class Buffering, class Coherence>
173 Cache<TagStore,Buffering,Coherence>::regStats()
175 BaseCache::regStats();
176 tags->regStats(name());
177 missQueue->regStats(name());
178 coherence->regStats(name());
179 prefetcher->regStats(name());
182 template<class TagStore, class Buffering, class Coherence>
184 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
186 //@todo Add back in MemDebug Calls
187 // MemDebug::cacheAccess(pkt);
189 PacketList writebacks;
191 int lat = hitLatency;
192 if (prefetchAccess) {
193 //We are determining prefetches on access stream, call prefetcher
194 prefetcher->handleMiss(pkt, curTick);
196 if (!pkt->req->isUncacheable()) {
197 blk = tags->handleAccess(pkt, lat, writebacks);
199 size = pkt->getSize();
201 // If this is a block size write/hint (WH64) allocate the block here
202 // if the coherence protocol allows it.
203 /** @todo make the fast write alloc (wh64) work with coherence. */
204 /** @todo Do we want to do fast writes for writebacks as well? */
205 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
206 (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
207 // not outstanding misses, can do this
208 MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
209 if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
210 if (outstanding_miss) {
211 warn("WriteInv doing a fastallocate"
212 "with an outstanding miss to the same address\n");
214 blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
219 while (!writebacks.empty()) {
220 missQueue->doWriteback(writebacks.front());
221 writebacks.pop_front();
223 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
224 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
225 pkt->getAddr() & ~((Addr)blkSize - 1));
228 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
229 // clear dirty bit if write through
230 if (pkt->needsResponse())
231 respond(pkt, curTick+lat);
232 if (pkt->cmd == Packet::Writeback) {
233 //Signal that you can kill the pkt/req
234 pkt->flags |= SATISFIED;
240 if (!pkt->req->isUncacheable()) {
241 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
242 /** @todo Move miss count code into BaseCache */
246 exitSimLoop("A cache reached the maximum miss count");
249 missQueue->handleMiss(pkt, size, curTick + hitLatency);
250 // return MA_CACHE_MISS;
255 template<class TagStore, class Buffering, class Coherence>
257 Cache<TagStore,Buffering,Coherence>::getPacket()
259 assert(missQueue->havePending());
260 Packet * pkt = missQueue->getPacket();
262 if (!pkt->req->isUncacheable()) {
263 if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
264 BlkType *blk = tags->findBlock(pkt);
265 Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
266 (blk)? blk->status : 0);
267 missQueue->setBusCmd(pkt, cmd);
271 assert(!doMasterRequest() || missQueue->havePending());
272 assert(!pkt || pkt->time <= curTick);
276 template<class TagStore, class Buffering, class Coherence>
278 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
280 if (success && !(pkt->flags & NACKED_LINE)) {
281 missQueue->markInService(pkt, mshr);
282 //Temp Hack for UPGRADES
283 if (pkt->cmd == Packet::UpgradeReq) {
284 pkt->flags &= ~CACHE_LINE_FILL;
285 BlkType *blk = tags->findBlock(pkt);
286 CacheBlk::State old_state = (blk) ? blk->status : 0;
287 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
288 if (old_state != new_state)
289 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
290 pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
291 //Set the state on the upgrade
292 memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
293 PacketList writebacks;
294 tags->handleFill(blk, mshr, new_state, writebacks, pkt);
295 assert(writebacks.empty());
296 missQueue->handleResponse(pkt, curTick + hitLatency);
298 } else if (pkt && !pkt->req->isUncacheable()) {
299 pkt->flags &= ~NACKED_LINE;
300 pkt->flags &= ~SATISFIED;
301 pkt->flags &= ~SNOOP_COMMIT;
302 missQueue->restoreOrigCmd(pkt);
306 template<class TagStore, class Buffering, class Coherence>
308 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
311 if (pkt->senderState) {
312 if (pkt->result == Packet::Nacked) {
313 //pkt->reinitFromRequest();
314 warn("NACKs from devices not connected to the same bus not implemented\n");
317 if (pkt->result == Packet::BadAddress) {
318 //Make the response a Bad address and send it
320 // MemDebug::cacheResponse(pkt);
321 DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
322 pkt->getAddr() & (((ULL(1))<<48)-1));
324 if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
325 blk = tags->findBlock(pkt);
326 CacheBlk::State old_state = (blk) ? blk->status : 0;
327 PacketList writebacks;
328 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
329 if (old_state != new_state)
330 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
331 pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
332 blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
333 new_state, writebacks, pkt);
334 while (!writebacks.empty()) {
335 missQueue->doWriteback(writebacks.front());
336 writebacks.pop_front();
339 missQueue->handleResponse(pkt, curTick + hitLatency);
343 template<class TagStore, class Buffering, class Coherence>
345 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
347 // Need to temporarily move this blk into MSHRs
348 MSHR *mshr = missQueue->allocateTargetList(addr);
351 // Read the data into the mshr
352 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
353 assert(dummy.empty());
354 assert(mshr->pkt->flags & SATISFIED);
355 // can overload order since it isn't used on non pending blocks
356 mshr->order = blk->status;
357 // temporarily remove the block from the cache.
358 tags->invalidateBlk(addr);
361 template<class TagStore, class Buffering, class Coherence>
363 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
365 // Need to temporarily move this blk into MSHRs
366 assert(mshr->pkt->cmd == Packet::ReadReq);
369 // Read the data into the mshr
370 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
371 assert(dummy.empty());
372 assert(mshr->pkt->flags & SATISFIED);
373 // can overload order since it isn't used on non pending blocks
374 mshr->order = blk->status;
375 // temporarily remove the block from the cache.
376 tags->invalidateBlk(mshr->pkt->getAddr());
380 template<class TagStore, class Buffering, class Coherence>
382 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
384 return coherence->getPacket();
388 template<class TagStore, class Buffering, class Coherence>
390 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
392 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
393 BlkType *blk = tags->findBlock(pkt);
394 MSHR *mshr = missQueue->findMSHR(blk_addr);
395 if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
396 //If we find an mshr, and it is in service, we need to NACK or invalidate
398 if (mshr->inService) {
399 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
400 && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
401 //If the outstanding request was an invalidate (upgrade,readex,..)
402 //Then we need to ACK the request until we get the data
403 //Also NACK if the outstanding request is not a cachefill (writeback)
404 assert(!(pkt->flags & SATISFIED));
405 pkt->flags |= SATISFIED;
406 pkt->flags |= NACKED_LINE;
407 ///@todo NACK's from other levels
408 //warn("NACKs from devices not connected to the same bus not implemented\n");
409 //respondToSnoop(pkt, curTick + hitLatency);
413 //The supplier will be someone else, because we are waiting for
414 //the data. This should cause this cache to be forced to go to
415 //the shared state, not the exclusive even though the shared line
416 //won't be asserted. But for now we will just invlidate ourselves
417 //and allow the other cache to go into the exclusive state.
418 //@todo Make it so a read to a pending read doesn't invalidate.
419 //@todo Make it so that a read to a pending read can't be exclusive now.
421 //Set the address so find match works
422 //panic("Don't have invalidates yet\n");
423 invalidatePkt->addrOverride(pkt->getAddr());
425 //Append the invalidate on
426 missQueue->addTarget(mshr,invalidatePkt);
427 DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
432 //We also need to check the writeback buffers and handle those
433 std::vector<MSHR *> writebacks;
434 if (missQueue->findWrites(blk_addr, writebacks)) {
435 DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
437 //Look through writebacks for any non-uncachable writes, use that
438 for (int i=0; i<writebacks.size(); i++) {
439 mshr = writebacks[i];
441 if (!mshr->pkt->req->isUncacheable()) {
443 //Only Upgrades don't get here
445 assert(!(pkt->flags & SATISFIED));
446 pkt->flags |= SATISFIED;
448 //If we are in an exclusive protocol, make it ask again
449 //to get write permissions (upgrade), signal shared
450 pkt->flags |= SHARED_LINE;
452 assert(pkt->isRead());
453 Addr offset = pkt->getAddr() & (blkSize - 1);
454 assert(offset < blkSize);
455 assert(pkt->getSize() <= blkSize);
456 assert(offset + pkt->getSize() <=blkSize);
457 memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
459 respondToSnoop(pkt, curTick + hitLatency);
462 if (pkt->isInvalidate()) {
463 //This must be an upgrade or other cache will take ownership
464 missQueue->markInService(mshr->pkt, mshr);
471 CacheBlk::State new_state;
472 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
474 DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
476 pkt->cmdString(), blk_addr, new_state);
478 tags->handleSnoop(blk, new_state, pkt);
479 respondToSnoop(pkt, curTick + hitLatency);
482 if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
483 pkt->cmdString(), blk_addr, new_state);
484 tags->handleSnoop(blk, new_state);
487 template<class TagStore, class Buffering, class Coherence>
489 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
491 //Need to handle the response, if NACKED
492 if (pkt->flags & NACKED_LINE) {
493 //Need to mark it as not in service, and retry for bus
494 assert(0); //Yeah, we saw a NACK come through
496 //For now this should never get called, we return false when we see a NACK
497 //instead, by doing this we allow the bus_blocked mechanism to handle the retry
498 //For now it retrys in just 2 cycles, need to figure out how to change that
499 //Eventually we will want to also have success come in as a parameter
500 //Need to make sure that we handle the functionality that happens on successufl
501 //return of the sendAddr function
505 template<class TagStore, class Buffering, class Coherence>
507 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
509 tags->invalidateBlk(addr);
514 * @todo Fix to not assume write allocate
516 template<class TagStore, class Buffering, class Coherence>
518 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
520 // MemDebug::cacheProbe(pkt);
521 if (!pkt->req->isUncacheable()) {
522 if (pkt->isInvalidate() && !pkt->isRead()
523 && !pkt->isWrite()) {
524 //Upgrade or Invalidate, satisfy it, don't forward
525 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
526 pkt->getAddr() & (((ULL(1))<<48)-1),
527 pkt->getAddr() & ~((Addr)blkSize - 1));
528 pkt->flags |= SATISFIED;
533 PacketList writebacks;
535 BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
537 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
538 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
539 pkt->getAddr() & ~((Addr)blkSize - 1));
542 // Need to check for outstanding misses and writes
543 Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
545 // There can only be one matching outstanding miss.
546 MSHR* mshr = missQueue->findMSHR(blk_addr);
548 // There can be many matching outstanding writes.
549 std::vector<MSHR*> writes;
550 missQueue->findWrites(blk_addr, writes);
553 otherSidePort->sendFunctional(pkt);
555 // Check for data in MSHR and writebuffer.
557 warn("Found outstanding miss on an non-update probe");
558 MSHR::TargetList *targets = mshr->getTargetList();
559 MSHR::TargetList::iterator i = targets->begin();
560 MSHR::TargetList::iterator end = targets->end();
561 for (; i != end; ++i) {
562 Packet * target = *i;
563 // If the target contains data, and it overlaps the
564 // probed request, need to update data
565 if (target->isWrite() && target->intersect(pkt)) {
569 if (target->getAddr() < pkt->getAddr()) {
570 int offset = pkt->getAddr() - target->getAddr();
571 pkt_data = pkt->getPtr<uint8_t>();
572 write_data = target->getPtr<uint8_t>() + offset;
573 data_size = target->getSize() - offset;
574 assert(data_size > 0);
575 if (data_size > pkt->getSize())
576 data_size = pkt->getSize();
578 int offset = target->getAddr() - pkt->getAddr();
579 pkt_data = pkt->getPtr<uint8_t>() + offset;
580 write_data = target->getPtr<uint8_t>();
581 data_size = pkt->getSize() - offset;
582 assert(data_size > pkt->getSize());
583 if (data_size > target->getSize())
584 data_size = target->getSize();
587 if (pkt->isWrite()) {
588 memcpy(pkt_data, write_data, data_size);
590 memcpy(write_data, pkt_data, data_size);
595 for (int i = 0; i < writes.size(); ++i) {
596 Packet * write = writes[i]->pkt;
597 if (write->intersect(pkt)) {
598 warn("Found outstanding write on an non-update probe");
602 if (write->getAddr() < pkt->getAddr()) {
603 int offset = pkt->getAddr() - write->getAddr();
604 pkt_data = pkt->getPtr<uint8_t>();
605 write_data = write->getPtr<uint8_t>() + offset;
606 data_size = write->getSize() - offset;
607 assert(data_size > 0);
608 if (data_size > pkt->getSize())
609 data_size = pkt->getSize();
611 int offset = write->getAddr() - pkt->getAddr();
612 pkt_data = pkt->getPtr<uint8_t>() + offset;
613 write_data = write->getPtr<uint8_t>();
614 data_size = pkt->getSize() - offset;
615 assert(data_size > pkt->getSize());
616 if (data_size > write->getSize())
617 data_size = write->getSize();
620 if (pkt->isWrite()) {
621 memcpy(pkt_data, write_data, data_size);
623 memcpy(write_data, pkt_data, data_size);
630 // update the cache state and statistics
631 if (mshr || !writes.empty()){
632 // Can't handle it, return pktuest unsatisfied.
633 panic("Atomic access ran into outstanding MSHR's or WB's!");
635 if (!pkt->req->isUncacheable()) {
636 // Fetch the cache block to fill
637 BlkType *blk = tags->findBlock(pkt);
638 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
639 (blk)? blk->status : 0);
641 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
645 busPkt->time = curTick;
647 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
649 busPkt->getAddr() & (((ULL(1))<<48)-1),
650 busPkt->getAddr() & ~((Addr)blkSize - 1));
652 lat = memSidePort->sendAtomic(busPkt);
654 //Be sure to flip the response to a request for coherence
655 if (busPkt->needsResponse()) {
656 busPkt->makeAtomicResponse();
659 /* if (!(busPkt->flags & SATISFIED)) {
660 // blocked at a higher level, just return
664 */ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
666 CacheBlk::State old_state = (blk) ? blk->status : 0;
667 CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
668 DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
670 busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
671 if (old_state != new_state)
672 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
673 busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
675 tags->handleFill(blk, busPkt,
681 // Handle writebacks if needed
682 while (!writebacks.empty()){
683 Packet *wbPkt = writebacks.front();
684 memSidePort->sendAtomic(wbPkt);
685 writebacks.pop_front();
688 return lat + hitLatency;
690 return memSidePort->sendAtomic(pkt);
694 // There was a cache hit.
695 // Handle writebacks if needed
696 while (!writebacks.empty()){
697 memSidePort->sendAtomic(writebacks.front());
698 writebacks.pop_front();
702 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
703 } else if (pkt->isWrite()) {
704 // Still need to change data in all locations.
705 otherSidePort->sendFunctional(pkt);
709 fatal("Probe not handled.\n");
713 template<class TagStore, class Buffering, class Coherence>
715 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
717 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
718 BlkType *blk = tags->findBlock(pkt);
719 MSHR *mshr = missQueue->findMSHR(blk_addr);
720 CacheBlk::State new_state = 0;
721 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
723 DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
725 pkt->cmdString(), blk_addr, new_state);
727 tags->handleSnoop(blk, new_state, pkt);
730 if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
731 pkt->cmdString(), blk_addr, new_state);
732 tags->handleSnoop(blk, new_state);