src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         access(pkt);
  67
  68     }
  69     else
  70     {
  71         if (pkt->isResponse())
  72             handleResponse(pkt);
  73         else {
  74             //Check if we should do the snoop
  75             if (pkt->flags & SNOOP_COMMIT)
  76                 snoop(pkt);
  77         }
  78     }
  79     return true;
  80 }
  81
  82 template<class TagStore, class Buffering, class Coherence>
  83 Tick
  84 Cache<TagStore,Buffering,Coherence>::
  85 doAtomicAccess(Packet *pkt, bool isCpuSide)
  86 {
  87     if (isCpuSide)
  88     {
  89         //Temporary solution to LL/SC
  90         if (pkt->isWrite() && (pkt->req->isLocked())) {
  91             pkt->req->setScResult(1);
  92         }
  93
  94         probe(pkt, true, NULL);
  95         //TEMP ALWAYS SUCCES FOR NOW
  96         pkt->result = Packet::Success;
  97     }
  98     else
  99     {
 100         if (pkt->isResponse())
 101             handleResponse(pkt);
 102         else
 103             snoopProbe(pkt);
 104     }
 105     //Fix this timing info
 106     return hitLatency;
 107 }
 108
 109 template<class TagStore, class Buffering, class Coherence>
 110 void
 111 Cache<TagStore,Buffering,Coherence>::
 112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 113 {
 114     if (isCpuSide)
 115     {
 116         //TEMP USE CPU?THREAD 0 0
 117         pkt->req->setThreadContext(0,0);
 118
 119         //Temporary solution to LL/SC
 120         if (pkt->isWrite() && (pkt->req->isLocked())) {
 121             assert("Can't handle LL/SC on functional path\n");
 122         }
 123
 124         probe(pkt, false, memSidePort);
 125         //TEMP ALWAYS SUCCESFUL FOR NOW
 126         pkt->result = Packet::Success;
 127     }
 128     else
 129     {
 130             probe(pkt, false, cpuSidePort);
 131     }
 132 }
 133
 134 template<class TagStore, class Buffering, class Coherence>
 135 void
 136 Cache<TagStore,Buffering,Coherence>::
 137 recvStatusChange(Port::Status status, bool isCpuSide)
 138 {
 139
 140 }
 141
 142
 143 template<class TagStore, class Buffering, class Coherence>
 144 Cache<TagStore,Buffering,Coherence>::
 145 Cache(const std::string &_name,
 146       Cache<TagStore,Buffering,Coherence>::Params &params)
 147     : BaseCache(_name, params.baseParams),
 148       prefetchAccess(params.prefetchAccess),
 149       tags(params.tags), missQueue(params.missQueue),
 150       coherence(params.coherence), prefetcher(params.prefetcher),
 151       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
 152 {
 153 //FIX BUS POINTERS
 154 //    if (params.in == NULL) {
 155         topLevelCache = true;
 156 //    }
 157 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
 158         tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
 159     tags->setPrefetcher(prefetcher);
 160     missQueue->setCache(this);
 161     missQueue->setPrefetcher(prefetcher);
 162     coherence->setCache(this);
 163     prefetcher->setCache(this);
 164     prefetcher->setTags(tags);
 165     prefetcher->setBuffer(missQueue);
 166     invalidateReq = new Request((Addr) NULL, blkSize, 0);
 167     invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
 168 }
 169
 170 template<class TagStore, class Buffering, class Coherence>
 171 void
 172 Cache<TagStore,Buffering,Coherence>::regStats()
 173 {
 174     BaseCache::regStats();
 175     tags->regStats(name());
 176     missQueue->regStats(name());
 177     coherence->regStats(name());
 178     prefetcher->regStats(name());
 179 }
 180
 181 template<class TagStore, class Buffering, class Coherence>
 182 bool
 183 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 184 {
 185 //@todo Add back in MemDebug Calls
 186 //    MemDebug::cacheAccess(pkt);
 187     BlkType *blk = NULL;
 188     PacketList writebacks;
 189     int size = blkSize;
 190     int lat = hitLatency;
 191     if (prefetchAccess) {
 192         //We are determining prefetches on access stream, call prefetcher
 193         prefetcher->handleMiss(pkt, curTick);
 194     }
 195     if (!pkt->req->isUncacheable()) {
 196         blk = tags->handleAccess(pkt, lat, writebacks);
 197     } else {
 198         size = pkt->getSize();
 199     }
 200     // If this is a block size write/hint (WH64) allocate the block here
 201     // if the coherence protocol allows it.
 202     /** @todo make the fast write alloc (wh64) work with coherence. */
 203     /** @todo Do we want to do fast writes for writebacks as well? */
 204     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 205         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 206         // not outstanding misses, can do this
 207         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 208         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 209             if (outstanding_miss) {
 210                 warn("WriteInv doing a fastallocate"
 211                      "with an outstanding miss to the same address\n");
 212             }
 213             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 214                                    writebacks);
 215             ++fastWrites;
 216         }
 217     }
 218     while (!writebacks.empty()) {
 219         missQueue->doWriteback(writebacks.front());
 220         writebacks.pop_front();
 221     }
 222     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 223             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 224             pkt->getAddr() & ~((Addr)blkSize - 1));
 225     if (blk) {
 226         // Hit
 227         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 228         // clear dirty bit if write through
 229         if (pkt->needsResponse())
 230             respond(pkt, curTick+lat);
 231         if (pkt->cmd == Packet::Writeback) {
 232             //Signal that you can kill the pkt/req
 233             pkt->flags |= SATISFIED;
 234         }
 235         return true;
 236     }
 237
 238     // Miss
 239     if (!pkt->req->isUncacheable()) {
 240         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 241         /** @todo Move miss count code into BaseCache */
 242         if (missCount) {
 243             --missCount;
 244             if (missCount == 0)
 245                 exitSimLoop("A cache reached the maximum miss count");
 246         }
 247     }
 248     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 249 //    return MA_CACHE_MISS;
 250     return true;
 251 }
 252
 253
 254 template<class TagStore, class Buffering, class Coherence>
 255 Packet *
 256 Cache<TagStore,Buffering,Coherence>::getPacket()
 257 {
 258     assert(missQueue->havePending());
 259     Packet * pkt = missQueue->getPacket();
 260     if (pkt) {
 261         if (!pkt->req->isUncacheable()) {
 262             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 263             BlkType *blk = tags->findBlock(pkt);
 264             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 265                                               (blk)? blk->status : 0);
 266             missQueue->setBusCmd(pkt, cmd);
 267         }
 268     }
 269
 270     assert(!doMasterRequest() || missQueue->havePending());
 271     assert(!pkt || pkt->time <= curTick);
 272     return pkt;
 273 }
 274
 275 template<class TagStore, class Buffering, class Coherence>
 276 void
 277 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
 278 {
 279     if (success && !(pkt->flags & NACKED_LINE)) {
 280         missQueue->markInService(pkt, mshr);
 281         //Temp Hack for UPGRADES
 282         if (pkt->cmd == Packet::UpgradeReq) {
 283             pkt->flags &= ~CACHE_LINE_FILL;
 284             BlkType *blk = tags->findBlock(pkt);
 285             CacheBlk::State old_state = (blk) ? blk->status : 0;
 286             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 287             DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 288                     pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 289             //Set the state on the upgrade
 290             memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
 291             PacketList writebacks;
 292             tags->handleFill(blk, mshr, new_state, writebacks, pkt);
 293             assert(writebacks.empty());
 294             missQueue->handleResponse(pkt, curTick + hitLatency);
 295         }
 296     } else if (pkt && !pkt->req->isUncacheable()) {
 297         pkt->flags &= ~NACKED_LINE;
 298         pkt->flags &= ~SATISFIED;
 299         pkt->flags &= ~SNOOP_COMMIT;
 300         missQueue->restoreOrigCmd(pkt);
 301     }
 302 }
 303
 304 template<class TagStore, class Buffering, class Coherence>
 305 void
 306 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 307 {
 308     BlkType *blk = NULL;
 309     if (pkt->senderState) {
 310         if (pkt->result == Packet::Nacked) {
 311             //pkt->reinitFromRequest();
 312             warn("NACKs from devices not connected to the same bus not implemented\n");
 313             return;
 314         }
 315         if (pkt->result == Packet::BadAddress) {
 316             //Make the response a Bad address and send it
 317         }
 318 //      MemDebug::cacheResponse(pkt);
 319         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 320                 pkt->getAddr() & (((ULL(1))<<48)-1));
 321
 322         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 323             blk = tags->findBlock(pkt);
 324             CacheBlk::State old_state = (blk) ? blk->status : 0;
 325             PacketList writebacks;
 326             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 327             DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 328                     pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 329             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 330                                    new_state, writebacks, pkt);
 331             while (!writebacks.empty()) {
 332                     missQueue->doWriteback(writebacks.front());
 333                     writebacks.pop_front();
 334             }
 335         }
 336         missQueue->handleResponse(pkt, curTick + hitLatency);
 337     }
 338 }
 339
 340 template<class TagStore, class Buffering, class Coherence>
 341 void
 342 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
 343 {
 344     // Need to temporarily move this blk into MSHRs
 345     MSHR *mshr = missQueue->allocateTargetList(addr);
 346     int lat;
 347     PacketList dummy;
 348     // Read the data into the mshr
 349     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 350     assert(dummy.empty());
 351     assert(mshr->pkt->flags & SATISFIED);
 352     // can overload order since it isn't used on non pending blocks
 353     mshr->order = blk->status;
 354     // temporarily remove the block from the cache.
 355     tags->invalidateBlk(addr);
 356 }
 357
 358 template<class TagStore, class Buffering, class Coherence>
 359 void
 360 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 361 {
 362     // Need to temporarily move this blk into MSHRs
 363     assert(mshr->pkt->cmd == Packet::ReadReq);
 364     int lat;
 365     PacketList dummy;
 366     // Read the data into the mshr
 367     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 368     assert(dummy.empty());
 369     assert(mshr->pkt->flags & SATISFIED);
 370     // can overload order since it isn't used on non pending blocks
 371     mshr->order = blk->status;
 372     // temporarily remove the block from the cache.
 373     tags->invalidateBlk(mshr->pkt->getAddr());
 374 }
 375
 376
 377 template<class TagStore, class Buffering, class Coherence>
 378 Packet *
 379 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 380 {
 381     return coherence->getPacket();
 382 }
 383
 384
 385 template<class TagStore, class Buffering, class Coherence>
 386 void
 387 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 388 {
 389     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 390     BlkType *blk = tags->findBlock(pkt);
 391     MSHR *mshr = missQueue->findMSHR(blk_addr);
 392     if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
 393         //If we find an mshr, and it is in service, we need to NACK or invalidate
 394         if (mshr) {
 395             if (mshr->inService) {
 396                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 397                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 398                     //If the outstanding request was an invalidate (upgrade,readex,..)
 399                     //Then we need to ACK the request until we get the data
 400                     //Also NACK if the outstanding request is not a cachefill (writeback)
 401                     assert(!(pkt->flags & SATISFIED));
 402                     pkt->flags |= SATISFIED;
 403                     pkt->flags |= NACKED_LINE;
 404                     ///@todo NACK's from other levels
 405                     //warn("NACKs from devices not connected to the same bus not implemented\n");
 406                     //respondToSnoop(pkt, curTick + hitLatency);
 407                     return;
 408                 }
 409                 else {
 410                     //The supplier will be someone else, because we are waiting for
 411                     //the data.  This should cause this cache to be forced to go to
 412                     //the shared state, not the exclusive even though the shared line
 413                     //won't be asserted.  But for now we will just invlidate ourselves
 414                     //and allow the other cache to go into the exclusive state.
 415                     //@todo Make it so a read to a pending read doesn't invalidate.
 416                     //@todo Make it so that a read to a pending read can't be exclusive now.
 417
 418                     //Set the address so find match works
 419                     //panic("Don't have invalidates yet\n");
 420                     invalidatePkt->addrOverride(pkt->getAddr());
 421
 422                     //Append the invalidate on
 423                     missQueue->addTarget(mshr,invalidatePkt);
 424                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 425                     return;
 426                 }
 427             }
 428         }
 429         //We also need to check the writeback buffers and handle those
 430         std::vector<MSHR *> writebacks;
 431         if (missQueue->findWrites(blk_addr, writebacks)) {
 432             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 433
 434             //Look through writebacks for any non-uncachable writes, use that
 435             for (int i=0; i<writebacks.size(); i++) {
 436                 mshr = writebacks[i];
 437
 438                 if (!mshr->pkt->req->isUncacheable()) {
 439                     if (pkt->isRead()) {
 440                         //Only Upgrades don't get here
 441                         //Supply the data
 442                         assert(!(pkt->flags & SATISFIED));
 443                         pkt->flags |= SATISFIED;
 444
 445                         //If we are in an exclusive protocol, make it ask again
 446                         //to get write permissions (upgrade), signal shared
 447                         pkt->flags |= SHARED_LINE;
 448
 449                         assert(pkt->isRead());
 450                         Addr offset = pkt->getAddr() & (blkSize - 1);
 451                         assert(offset < blkSize);
 452                         assert(pkt->getSize() <= blkSize);
 453                         assert(offset + pkt->getSize() <=blkSize);
 454                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 455
 456                         respondToSnoop(pkt, curTick + hitLatency);
 457                     }
 458
 459                     if (pkt->isInvalidate()) {
 460                         //This must be an upgrade or other cache will take ownership
 461                         missQueue->markInService(mshr->pkt, mshr);
 462                     }
 463                     return;
 464                 }
 465             }
 466         }
 467     }
 468     CacheBlk::State new_state;
 469     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 470     if (satisfy) {
 471         DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 472                 "new state is %i\n",
 473                 pkt->cmdString(), blk_addr, new_state);
 474
 475         tags->handleSnoop(blk, new_state, pkt);
 476         respondToSnoop(pkt, curTick + hitLatency);
 477         return;
 478     }
 479     if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 480                      pkt->cmdString(), blk_addr, new_state);
 481     tags->handleSnoop(blk, new_state);
 482 }
 483
 484 template<class TagStore, class Buffering, class Coherence>
 485 void
 486 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 487 {
 488     //Need to handle the response, if NACKED
 489     if (pkt->flags & NACKED_LINE) {
 490         //Need to mark it as not in service, and retry for bus
 491         assert(0); //Yeah, we saw a NACK come through
 492
 493         //For now this should never get called, we return false when we see a NACK
 494         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 495         //For now it retrys in just 2 cycles, need to figure out how to change that
 496         //Eventually we will want to also have success come in as a parameter
 497         //Need to make sure that we handle the functionality that happens on successufl
 498         //return of the sendAddr function
 499     }
 500 }
 501
 502 template<class TagStore, class Buffering, class Coherence>
 503 void
 504 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 505 {
 506     tags->invalidateBlk(addr);
 507 }
 508
 509
 510 /**
 511  * @todo Fix to not assume write allocate
 512  */
 513 template<class TagStore, class Buffering, class Coherence>
 514 Tick
 515 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
 516 {
 517 //    MemDebug::cacheProbe(pkt);
 518     if (!pkt->req->isUncacheable()) {
 519         if (pkt->isInvalidate() && !pkt->isRead()
 520             && !pkt->isWrite()) {
 521             //Upgrade or Invalidate, satisfy it, don't forward
 522             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 523                     pkt->getAddr() & (((ULL(1))<<48)-1),
 524                     pkt->getAddr() & ~((Addr)blkSize - 1));
 525             pkt->flags |= SATISFIED;
 526             return 0;
 527         }
 528     }
 529
 530     PacketList writebacks;
 531     int lat;
 532     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 533
 534     if (!blk) {
 535         // Need to check for outstanding misses and writes
 536         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 537
 538         // There can only be one matching outstanding miss.
 539         MSHR* mshr = missQueue->findMSHR(blk_addr);
 540
 541         // There can be many matching outstanding writes.
 542         std::vector<MSHR*> writes;
 543         missQueue->findWrites(blk_addr, writes);
 544
 545         if (!update) {
 546                 otherSidePort->sendFunctional(pkt);
 547
 548             // Check for data in MSHR and writebuffer.
 549             if (mshr) {
 550                 warn("Found outstanding miss on an non-update probe");
 551                 MSHR::TargetList *targets = mshr->getTargetList();
 552                 MSHR::TargetList::iterator i = targets->begin();
 553                 MSHR::TargetList::iterator end = targets->end();
 554                 for (; i != end; ++i) {
 555                     Packet * target = *i;
 556                     // If the target contains data, and it overlaps the
 557                     // probed request, need to update data
 558                     if (target->isWrite() && target->intersect(pkt)) {
 559                         uint8_t* pkt_data;
 560                         uint8_t* write_data;
 561                         int data_size;
 562                         if (target->getAddr() < pkt->getAddr()) {
 563                             int offset = pkt->getAddr() - target->getAddr();
 564                             pkt_data = pkt->getPtr<uint8_t>();
 565                             write_data = target->getPtr<uint8_t>() + offset;
 566                             data_size = target->getSize() - offset;
 567                             assert(data_size > 0);
 568                             if (data_size > pkt->getSize())
 569                                 data_size = pkt->getSize();
 570                         } else {
 571                             int offset = target->getAddr() - pkt->getAddr();
 572                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 573                             write_data = target->getPtr<uint8_t>();
 574                             data_size = pkt->getSize() - offset;
 575                             assert(data_size > pkt->getSize());
 576                             if (data_size > target->getSize())
 577                                 data_size = target->getSize();
 578                         }
 579
 580                         if (pkt->isWrite()) {
 581                             memcpy(pkt_data, write_data, data_size);
 582                         } else {
 583                             memcpy(write_data, pkt_data, data_size);
 584                         }
 585                     }
 586                 }
 587             }
 588             for (int i = 0; i < writes.size(); ++i) {
 589                 Packet * write = writes[i]->pkt;
 590                 if (write->intersect(pkt)) {
 591                     warn("Found outstanding write on an non-update probe");
 592                     uint8_t* pkt_data;
 593                     uint8_t* write_data;
 594                     int data_size;
 595                     if (write->getAddr() < pkt->getAddr()) {
 596                         int offset = pkt->getAddr() - write->getAddr();
 597                         pkt_data = pkt->getPtr<uint8_t>();
 598                         write_data = write->getPtr<uint8_t>() + offset;
 599                         data_size = write->getSize() - offset;
 600                         assert(data_size > 0);
 601                         if (data_size > pkt->getSize())
 602                             data_size = pkt->getSize();
 603                     } else {
 604                         int offset = write->getAddr() - pkt->getAddr();
 605                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 606                         write_data = write->getPtr<uint8_t>();
 607                         data_size = pkt->getSize() - offset;
 608                         assert(data_size > pkt->getSize());
 609                         if (data_size > write->getSize())
 610                             data_size = write->getSize();
 611                     }
 612
 613                     if (pkt->isWrite()) {
 614                         memcpy(pkt_data, write_data, data_size);
 615                     } else {
 616                         memcpy(write_data, pkt_data, data_size);
 617                     }
 618
 619                 }
 620             }
 621             return 0;
 622         } else {
 623             // update the cache state and statistics
 624             if (mshr || !writes.empty()){
 625                 // Can't handle it, return pktuest unsatisfied.
 626                 panic("Atomic access ran into outstanding MSHR's or WB's!");
 627             }
 628             if (!pkt->req->isUncacheable()) {
 629                 // Fetch the cache block to fill
 630                 BlkType *blk = tags->findBlock(pkt);
 631                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 632                                                    (blk)? blk->status : 0);
 633
 634                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 635
 636                 busPkt->allocate();
 637
 638                 busPkt->time = curTick;
 639
 640                 lat = memSidePort->sendAtomic(busPkt);
 641
 642                 //Be sure to flip the response to a request for coherence
 643                 if (busPkt->needsResponse()) {
 644                     busPkt->makeAtomicResponse();
 645                 }
 646
 647 /*              if (!(busPkt->flags & SATISFIED)) {
 648                     // blocked at a higher level, just return
 649                     return 0;
 650                 }
 651
 652 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 653
 654                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 655                 tags->handleFill(blk, busPkt,
 656                                  coherence->getNewState(busPkt, old_state),
 657                                  writebacks, pkt);
 658                 // Handle writebacks if needed
 659                 while (!writebacks.empty()){
 660                     memSidePort->sendAtomic(writebacks.front());
 661                     writebacks.pop_front();
 662                 }
 663                 return lat + hitLatency;
 664             } else {
 665                 return memSidePort->sendAtomic(pkt);
 666             }
 667         }
 668     } else {
 669         // There was a cache hit.
 670         // Handle writebacks if needed
 671         while (!writebacks.empty()){
 672             memSidePort->sendAtomic(writebacks.front());
 673             writebacks.pop_front();
 674         }
 675
 676         if (update) {
 677             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 678         } else if (pkt->isWrite()) {
 679             // Still need to change data in all locations.
 680             otherSidePort->sendFunctional(pkt);
 681         }
 682         return curTick + lat;
 683     }
 684     fatal("Probe not handled.\n");
 685     return 0;
 686 }
 687
 688 template<class TagStore, class Buffering, class Coherence>
 689 Tick
 690 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 691 {
 692         Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 693         BlkType *blk = tags->findBlock(pkt);
 694         MSHR *mshr = missQueue->findMSHR(blk_addr);
 695         CacheBlk::State new_state = 0;
 696         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 697         if (satisfy) {
 698             DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
 699                     "new state is %i\n",
 700                     pkt->cmdString(), blk_addr, new_state);
 701
 702             tags->handleSnoop(blk, new_state, pkt);
 703             return hitLatency;
 704         }
 705         if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
 706                      pkt->cmdString(), blk_addr, new_state);
 707         tags->handleSnoop(blk, new_state);
 708         return 0;
 709 }
 710