2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
45 #include "sim/host.hh"
46 #include "base/misc.hh"
49 #include "mem/cache/cache.hh"
50 #include "mem/cache/cache_blk.hh"
51 #include "mem/cache/miss/mshr.hh"
52 #include "mem/cache/prefetch/prefetcher.hh"
54 #include "sim/sim_exit.hh" // for SimExitEvent
56 template<class TagStore, class Buffering, class Coherence>
58 Cache<TagStore,Buffering,Coherence>::
59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
63 if (pkt->isWrite() && (pkt->req->isLocked())) {
64 pkt->req->setScResult(1);
71 if (pkt->isResponse())
74 //Check if we should do the snoop
75 if (pkt->flags & SNOOP_COMMIT)
82 template<class TagStore, class Buffering, class Coherence>
84 Cache<TagStore,Buffering,Coherence>::
85 doAtomicAccess(Packet *pkt, bool isCpuSide)
89 //Temporary solution to LL/SC
90 if (pkt->isWrite() && (pkt->req->isLocked())) {
91 pkt->req->setScResult(1);
94 probe(pkt, true, NULL);
95 //TEMP ALWAYS SUCCES FOR NOW
96 pkt->result = Packet::Success;
100 if (pkt->isResponse())
103 return snoopProbe(pkt);
105 //Fix this timing info
109 template<class TagStore, class Buffering, class Coherence>
111 Cache<TagStore,Buffering,Coherence>::
112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
116 //TEMP USE CPU?THREAD 0 0
117 pkt->req->setThreadContext(0,0);
119 //Temporary solution to LL/SC
120 if (pkt->isWrite() && (pkt->req->isLocked())) {
121 assert("Can't handle LL/SC on functional path\n");
124 probe(pkt, false, memSidePort);
125 //TEMP ALWAYS SUCCESFUL FOR NOW
126 pkt->result = Packet::Success;
130 probe(pkt, false, cpuSidePort);
134 template<class TagStore, class Buffering, class Coherence>
136 Cache<TagStore,Buffering,Coherence>::
137 recvStatusChange(Port::Status status, bool isCpuSide)
143 template<class TagStore, class Buffering, class Coherence>
144 Cache<TagStore,Buffering,Coherence>::
145 Cache(const std::string &_name,
146 Cache<TagStore,Buffering,Coherence>::Params ¶ms)
147 : BaseCache(_name, params.baseParams),
148 prefetchAccess(params.prefetchAccess),
149 tags(params.tags), missQueue(params.missQueue),
150 coherence(params.coherence), prefetcher(params.prefetcher),
151 doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
152 hitLatency(params.hitLatency)
155 // if (params.in == NULL) {
156 topLevelCache = true;
158 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
159 tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
160 tags->setPrefetcher(prefetcher);
161 missQueue->setCache(this);
162 missQueue->setPrefetcher(prefetcher);
163 coherence->setCache(this);
164 prefetcher->setCache(this);
165 prefetcher->setTags(tags);
166 prefetcher->setBuffer(missQueue);
167 invalidateReq = new Request((Addr) NULL, blkSize, 0);
168 invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
171 template<class TagStore, class Buffering, class Coherence>
173 Cache<TagStore,Buffering,Coherence>::regStats()
175 BaseCache::regStats();
176 tags->regStats(name());
177 missQueue->regStats(name());
178 coherence->regStats(name());
179 prefetcher->regStats(name());
182 template<class TagStore, class Buffering, class Coherence>
184 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
186 //@todo Add back in MemDebug Calls
187 // MemDebug::cacheAccess(pkt);
189 PacketList writebacks;
191 int lat = hitLatency;
192 if (prefetchAccess) {
193 //We are determining prefetches on access stream, call prefetcher
194 prefetcher->handleMiss(pkt, curTick);
196 if (!pkt->req->isUncacheable()) {
197 blk = tags->handleAccess(pkt, lat, writebacks);
199 size = pkt->getSize();
201 // If this is a block size write/hint (WH64) allocate the block here
202 // if the coherence protocol allows it.
203 /** @todo make the fast write alloc (wh64) work with coherence. */
204 /** @todo Do we want to do fast writes for writebacks as well? */
205 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
206 (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
207 // not outstanding misses, can do this
208 MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
209 if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
210 if (outstanding_miss) {
211 warn("WriteInv doing a fastallocate"
212 "with an outstanding miss to the same address\n");
214 blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
219 while (!writebacks.empty()) {
220 missQueue->doWriteback(writebacks.front());
221 writebacks.pop_front();
223 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
224 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
225 pkt->getAddr() & ~((Addr)blkSize - 1));
228 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
229 // clear dirty bit if write through
230 if (pkt->needsResponse())
231 respond(pkt, curTick+lat);
232 if (pkt->cmd == Packet::Writeback) {
233 //Signal that you can kill the pkt/req
234 pkt->flags |= SATISFIED;
240 if (!pkt->req->isUncacheable()) {
241 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
242 /** @todo Move miss count code into BaseCache */
246 exitSimLoop("A cache reached the maximum miss count");
249 missQueue->handleMiss(pkt, size, curTick + hitLatency);
250 // return MA_CACHE_MISS;
255 template<class TagStore, class Buffering, class Coherence>
257 Cache<TagStore,Buffering,Coherence>::getPacket()
259 assert(missQueue->havePending());
260 Packet * pkt = missQueue->getPacket();
262 if (!pkt->req->isUncacheable()) {
263 if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
264 BlkType *blk = tags->findBlock(pkt);
265 Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
266 (blk)? blk->status : 0);
267 missQueue->setBusCmd(pkt, cmd);
271 assert(!doMasterRequest() || missQueue->havePending());
272 assert(!pkt || pkt->time <= curTick);
276 template<class TagStore, class Buffering, class Coherence>
278 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
280 if (success && !(pkt->flags & NACKED_LINE)) {
281 missQueue->markInService(pkt, mshr);
282 //Temp Hack for UPGRADES
283 if (pkt->cmd == Packet::UpgradeReq) {
284 pkt->flags &= ~CACHE_LINE_FILL;
285 BlkType *blk = tags->findBlock(pkt);
286 CacheBlk::State old_state = (blk) ? blk->status : 0;
287 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
288 if (old_state != new_state)
289 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
290 pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
291 //Set the state on the upgrade
292 memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
293 PacketList writebacks;
294 tags->handleFill(blk, mshr, new_state, writebacks, pkt);
295 assert(writebacks.empty());
296 missQueue->handleResponse(pkt, curTick + hitLatency);
298 } else if (pkt && !pkt->req->isUncacheable()) {
299 pkt->flags &= ~NACKED_LINE;
300 pkt->flags &= ~SATISFIED;
301 pkt->flags &= ~SNOOP_COMMIT;
302 missQueue->restoreOrigCmd(pkt);
306 template<class TagStore, class Buffering, class Coherence>
308 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
311 if (pkt->senderState) {
312 if (pkt->result == Packet::Nacked) {
313 //pkt->reinitFromRequest();
314 warn("NACKs from devices not connected to the same bus not implemented\n");
317 if (pkt->result == Packet::BadAddress) {
318 //Make the response a Bad address and send it
320 // MemDebug::cacheResponse(pkt);
321 DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
322 pkt->getAddr() & (((ULL(1))<<48)-1));
324 if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
325 blk = tags->findBlock(pkt);
326 CacheBlk::State old_state = (blk) ? blk->status : 0;
327 PacketList writebacks;
328 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
329 if (old_state != new_state)
330 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
331 pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
332 blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
333 new_state, writebacks, pkt);
334 while (!writebacks.empty()) {
335 missQueue->doWriteback(writebacks.front());
336 writebacks.pop_front();
339 missQueue->handleResponse(pkt, curTick + hitLatency);
343 template<class TagStore, class Buffering, class Coherence>
345 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
347 // Need to temporarily move this blk into MSHRs
348 MSHR *mshr = missQueue->allocateTargetList(addr);
351 // Read the data into the mshr
352 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
353 assert(dummy.empty());
354 assert(mshr->pkt->flags & SATISFIED);
355 // can overload order since it isn't used on non pending blocks
356 mshr->order = blk->status;
357 // temporarily remove the block from the cache.
358 tags->invalidateBlk(addr);
361 template<class TagStore, class Buffering, class Coherence>
363 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
365 // Need to temporarily move this blk into MSHRs
366 assert(mshr->pkt->cmd == Packet::ReadReq);
369 // Read the data into the mshr
370 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
371 assert(dummy.empty());
372 assert(mshr->pkt->flags & SATISFIED);
373 // can overload order since it isn't used on non pending blocks
374 mshr->order = blk->status;
375 // temporarily remove the block from the cache.
376 tags->invalidateBlk(mshr->pkt->getAddr());
380 template<class TagStore, class Buffering, class Coherence>
382 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
384 return coherence->getPacket();
388 template<class TagStore, class Buffering, class Coherence>
390 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
392 if (pkt->req->isUncacheable()) {
393 //Can't get a hit on an uncacheable address
394 //Revisit this for multi level coherence
397 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
398 BlkType *blk = tags->findBlock(pkt);
399 MSHR *mshr = missQueue->findMSHR(blk_addr);
400 if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
401 //If we find an mshr, and it is in service, we need to NACK or invalidate
403 if (mshr->inService) {
404 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
405 && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
406 //If the outstanding request was an invalidate (upgrade,readex,..)
407 //Then we need to ACK the request until we get the data
408 //Also NACK if the outstanding request is not a cachefill (writeback)
409 assert(!(pkt->flags & SATISFIED));
410 pkt->flags |= SATISFIED;
411 pkt->flags |= NACKED_LINE;
412 ///@todo NACK's from other levels
413 //warn("NACKs from devices not connected to the same bus not implemented\n");
414 //respondToSnoop(pkt, curTick + hitLatency);
418 //The supplier will be someone else, because we are waiting for
419 //the data. This should cause this cache to be forced to go to
420 //the shared state, not the exclusive even though the shared line
421 //won't be asserted. But for now we will just invlidate ourselves
422 //and allow the other cache to go into the exclusive state.
423 //@todo Make it so a read to a pending read doesn't invalidate.
424 //@todo Make it so that a read to a pending read can't be exclusive now.
426 //Set the address so find match works
427 //panic("Don't have invalidates yet\n");
428 invalidatePkt->addrOverride(pkt->getAddr());
430 //Append the invalidate on
431 missQueue->addTarget(mshr,invalidatePkt);
432 DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
437 //We also need to check the writeback buffers and handle those
438 std::vector<MSHR *> writebacks;
439 if (missQueue->findWrites(blk_addr, writebacks)) {
440 DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
442 //Look through writebacks for any non-uncachable writes, use that
443 for (int i=0; i<writebacks.size(); i++) {
444 mshr = writebacks[i];
446 if (!mshr->pkt->req->isUncacheable()) {
448 //Only Upgrades don't get here
450 assert(!(pkt->flags & SATISFIED));
451 pkt->flags |= SATISFIED;
453 //If we are in an exclusive protocol, make it ask again
454 //to get write permissions (upgrade), signal shared
455 pkt->flags |= SHARED_LINE;
457 assert(pkt->isRead());
458 Addr offset = pkt->getAddr() & (blkSize - 1);
459 assert(offset < blkSize);
460 assert(pkt->getSize() <= blkSize);
461 assert(offset + pkt->getSize() <=blkSize);
462 memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
464 respondToSnoop(pkt, curTick + hitLatency);
467 if (pkt->isInvalidate()) {
468 //This must be an upgrade or other cache will take ownership
469 missQueue->markInService(mshr->pkt, mshr);
476 CacheBlk::State new_state;
477 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
479 DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
481 pkt->cmdString(), blk_addr, new_state);
483 tags->handleSnoop(blk, new_state, pkt);
484 respondToSnoop(pkt, curTick + hitLatency);
487 if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
488 pkt->cmdString(), blk_addr, new_state);
489 tags->handleSnoop(blk, new_state);
492 template<class TagStore, class Buffering, class Coherence>
494 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
496 //Need to handle the response, if NACKED
497 if (pkt->flags & NACKED_LINE) {
498 //Need to mark it as not in service, and retry for bus
499 assert(0); //Yeah, we saw a NACK come through
501 //For now this should never get called, we return false when we see a NACK
502 //instead, by doing this we allow the bus_blocked mechanism to handle the retry
503 //For now it retrys in just 2 cycles, need to figure out how to change that
504 //Eventually we will want to also have success come in as a parameter
505 //Need to make sure that we handle the functionality that happens on successufl
506 //return of the sendAddr function
510 template<class TagStore, class Buffering, class Coherence>
512 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
514 tags->invalidateBlk(addr);
519 * @todo Fix to not assume write allocate
521 template<class TagStore, class Buffering, class Coherence>
523 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
525 // MemDebug::cacheProbe(pkt);
526 if (!pkt->req->isUncacheable()) {
527 if (pkt->isInvalidate() && !pkt->isRead()
528 && !pkt->isWrite()) {
529 //Upgrade or Invalidate, satisfy it, don't forward
530 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
531 pkt->getAddr() & (((ULL(1))<<48)-1),
532 pkt->getAddr() & ~((Addr)blkSize - 1));
533 pkt->flags |= SATISFIED;
538 PacketList writebacks;
540 BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
542 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
543 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
544 pkt->getAddr() & ~((Addr)blkSize - 1));
547 // Need to check for outstanding misses and writes
548 Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
550 // There can only be one matching outstanding miss.
551 MSHR* mshr = missQueue->findMSHR(blk_addr);
553 // There can be many matching outstanding writes.
554 std::vector<MSHR*> writes;
555 missQueue->findWrites(blk_addr, writes);
558 otherSidePort->sendFunctional(pkt);
560 // Check for data in MSHR and writebuffer.
562 warn("Found outstanding miss on an non-update probe");
563 MSHR::TargetList *targets = mshr->getTargetList();
564 MSHR::TargetList::iterator i = targets->begin();
565 MSHR::TargetList::iterator end = targets->end();
566 for (; i != end; ++i) {
567 Packet * target = *i;
568 // If the target contains data, and it overlaps the
569 // probed request, need to update data
570 if (target->isWrite() && target->intersect(pkt)) {
574 if (target->getAddr() < pkt->getAddr()) {
575 int offset = pkt->getAddr() - target->getAddr();
576 pkt_data = pkt->getPtr<uint8_t>();
577 write_data = target->getPtr<uint8_t>() + offset;
578 data_size = target->getSize() - offset;
579 assert(data_size > 0);
580 if (data_size > pkt->getSize())
581 data_size = pkt->getSize();
583 int offset = target->getAddr() - pkt->getAddr();
584 pkt_data = pkt->getPtr<uint8_t>() + offset;
585 write_data = target->getPtr<uint8_t>();
586 data_size = pkt->getSize() - offset;
587 assert(data_size > pkt->getSize());
588 if (data_size > target->getSize())
589 data_size = target->getSize();
592 if (pkt->isWrite()) {
593 memcpy(pkt_data, write_data, data_size);
595 memcpy(write_data, pkt_data, data_size);
600 for (int i = 0; i < writes.size(); ++i) {
601 Packet * write = writes[i]->pkt;
602 if (write->intersect(pkt)) {
603 warn("Found outstanding write on an non-update probe");
607 if (write->getAddr() < pkt->getAddr()) {
608 int offset = pkt->getAddr() - write->getAddr();
609 pkt_data = pkt->getPtr<uint8_t>();
610 write_data = write->getPtr<uint8_t>() + offset;
611 data_size = write->getSize() - offset;
612 assert(data_size > 0);
613 if (data_size > pkt->getSize())
614 data_size = pkt->getSize();
616 int offset = write->getAddr() - pkt->getAddr();
617 pkt_data = pkt->getPtr<uint8_t>() + offset;
618 write_data = write->getPtr<uint8_t>();
619 data_size = pkt->getSize() - offset;
620 assert(data_size > pkt->getSize());
621 if (data_size > write->getSize())
622 data_size = write->getSize();
625 if (pkt->isWrite()) {
626 memcpy(pkt_data, write_data, data_size);
628 memcpy(write_data, pkt_data, data_size);
635 // update the cache state and statistics
636 if (mshr || !writes.empty()){
637 // Can't handle it, return pktuest unsatisfied.
638 panic("Atomic access ran into outstanding MSHR's or WB's!");
640 if (!pkt->req->isUncacheable()) {
641 // Fetch the cache block to fill
642 BlkType *blk = tags->findBlock(pkt);
643 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
644 (blk)? blk->status : 0);
646 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
650 busPkt->time = curTick;
652 DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
654 busPkt->getAddr() & (((ULL(1))<<48)-1),
655 busPkt->getAddr() & ~((Addr)blkSize - 1));
657 lat = memSidePort->sendAtomic(busPkt);
659 //Be sure to flip the response to a request for coherence
660 if (busPkt->needsResponse()) {
661 busPkt->makeAtomicResponse();
664 /* if (!(busPkt->flags & SATISFIED)) {
665 // blocked at a higher level, just return
669 */ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
671 CacheBlk::State old_state = (blk) ? blk->status : 0;
672 CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
673 DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
675 busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
676 if (old_state != new_state)
677 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
678 busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
680 tags->handleFill(blk, busPkt,
686 // Handle writebacks if needed
687 while (!writebacks.empty()){
688 Packet *wbPkt = writebacks.front();
689 memSidePort->sendAtomic(wbPkt);
690 writebacks.pop_front();
693 return lat + hitLatency;
695 return memSidePort->sendAtomic(pkt);
699 // There was a cache hit.
700 // Handle writebacks if needed
701 while (!writebacks.empty()){
702 memSidePort->sendAtomic(writebacks.front());
703 writebacks.pop_front();
707 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
708 } else if (pkt->isWrite()) {
709 // Still need to change data in all locations.
710 otherSidePort->sendFunctional(pkt);
714 fatal("Probe not handled.\n");
718 template<class TagStore, class Buffering, class Coherence>
720 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
722 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
723 BlkType *blk = tags->findBlock(pkt);
724 MSHR *mshr = missQueue->findMSHR(blk_addr);
725 CacheBlk::State new_state = 0;
726 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
728 DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
730 pkt->cmdString(), blk_addr, new_state);
732 tags->handleSnoop(blk, new_state, pkt);
735 if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
736 pkt->cmdString(), blk_addr, new_state);
737 tags->handleSnoop(blk, new_state);