src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_exit.hh" // for SimExitEvent
  55
  56 template<class TagStore, class Buffering, class Coherence>
  57 bool
  58 Cache<TagStore,Buffering,Coherence>::
  59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  60 {
  61     if (isCpuSide)
  62     {
  63         if (pkt->isWrite() && (pkt->req->isLocked())) {
  64             pkt->req->setScResult(1);
  65         }
  66         if (!(pkt->flags & SATISFIED)) {
  67             access(pkt);
  68         }
  69     }
  70     else
  71     {
  72         if (pkt->isResponse())
  73             handleResponse(pkt);
  74         else {
  75             //Check if we should do the snoop
  76             if (pkt->flags & SNOOP_COMMIT)
  77                 snoop(pkt);
  78         }
  79     }
  80     return true;
  81 }
  82
  83 template<class TagStore, class Buffering, class Coherence>
  84 Tick
  85 Cache<TagStore,Buffering,Coherence>::
  86 doAtomicAccess(Packet *pkt, bool isCpuSide)
  87 {
  88     if (isCpuSide)
  89     {
  90         //Temporary solution to LL/SC
  91         if (pkt->isWrite() && (pkt->req->isLocked())) {
  92             pkt->req->setScResult(1);
  93         }
  94
  95         probe(pkt, true, NULL);
  96         //TEMP ALWAYS SUCCES FOR NOW
  97         pkt->result = Packet::Success;
  98     }
  99     else
 100     {
 101         if (pkt->isResponse())
 102             handleResponse(pkt);
 103         else
 104             snoopProbe(pkt);
 105     }
 106     //Fix this timing info
 107     return hitLatency;
 108 }
 109
 110 template<class TagStore, class Buffering, class Coherence>
 111 void
 112 Cache<TagStore,Buffering,Coherence>::
 113 doFunctionalAccess(Packet *pkt, bool isCpuSide)
 114 {
 115     if (isCpuSide)
 116     {
 117         //TEMP USE CPU?THREAD 0 0
 118         pkt->req->setThreadContext(0,0);
 119
 120         //Temporary solution to LL/SC
 121         if (pkt->isWrite() && (pkt->req->isLocked())) {
 122             assert("Can't handle LL/SC on functional path\n");
 123         }
 124
 125         probe(pkt, false, memSidePort);
 126         //TEMP ALWAYS SUCCESFUL FOR NOW
 127         pkt->result = Packet::Success;
 128     }
 129     else
 130     {
 131             probe(pkt, false, cpuSidePort);
 132     }
 133 }
 134
 135 template<class TagStore, class Buffering, class Coherence>
 136 void
 137 Cache<TagStore,Buffering,Coherence>::
 138 recvStatusChange(Port::Status status, bool isCpuSide)
 139 {
 140
 141 }
 142
 143
 144 template<class TagStore, class Buffering, class Coherence>
 145 Cache<TagStore,Buffering,Coherence>::
 146 Cache(const std::string &_name,
 147       Cache<TagStore,Buffering,Coherence>::Params &params)
 148     : BaseCache(_name, params.baseParams),
 149       prefetchAccess(params.prefetchAccess),
 150       tags(params.tags), missQueue(params.missQueue),
 151       coherence(params.coherence), prefetcher(params.prefetcher),
 152       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
 153 {
 154 //FIX BUS POINTERS
 155 //    if (params.in == NULL) {
 156         topLevelCache = true;
 157 //    }
 158 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
 159         tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
 160     tags->setPrefetcher(prefetcher);
 161     missQueue->setCache(this);
 162     missQueue->setPrefetcher(prefetcher);
 163     coherence->setCache(this);
 164     prefetcher->setCache(this);
 165     prefetcher->setTags(tags);
 166     prefetcher->setBuffer(missQueue);
 167 #if 0
 168     invalidatePkt = new Packet;
 169     invalidatePkt->cmd = Packet::InvalidateReq;
 170 #endif
 171 }
 172
 173 template<class TagStore, class Buffering, class Coherence>
 174 void
 175 Cache<TagStore,Buffering,Coherence>::regStats()
 176 {
 177     BaseCache::regStats();
 178     tags->regStats(name());
 179     missQueue->regStats(name());
 180     coherence->regStats(name());
 181     prefetcher->regStats(name());
 182 }
 183
 184 template<class TagStore, class Buffering, class Coherence>
 185 bool
 186 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 187 {
 188 //@todo Add back in MemDebug Calls
 189 //    MemDebug::cacheAccess(pkt);
 190     BlkType *blk = NULL;
 191     PacketList writebacks;
 192     int size = blkSize;
 193     int lat = hitLatency;
 194     if (prefetchAccess) {
 195         //We are determining prefetches on access stream, call prefetcher
 196         prefetcher->handleMiss(pkt, curTick);
 197     }
 198     if (!pkt->req->isUncacheable()) {
 199         if (pkt->isInvalidate() && !pkt->isRead()
 200             && !pkt->isWrite()) {
 201             //Upgrade or Invalidate
 202             //Look into what happens if two slave caches on bus
 203             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 204                     pkt->getAddr() & (((ULL(1))<<48)-1),
 205                     pkt->getAddr() & ~((Addr)blkSize - 1));
 206
 207             //@todo Should this return latency have the hit latency in it?
 208 //          respond(pkt,curTick+lat);
 209             pkt->flags |= SATISFIED;
 210 //            return MA_HIT; //@todo, return values
 211             return true;
 212         }
 213         blk = tags->handleAccess(pkt, lat, writebacks);
 214     } else {
 215         size = pkt->getSize();
 216     }
 217     // If this is a block size write/hint (WH64) allocate the block here
 218     // if the coherence protocol allows it.
 219     /** @todo make the fast write alloc (wh64) work with coherence. */
 220     /** @todo Do we want to do fast writes for writebacks as well? */
 221     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 222         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 223         // not outstanding misses, can do this
 224         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
 225         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 226             if (outstanding_miss) {
 227                 warn("WriteInv doing a fastallocate"
 228                      "with an outstanding miss to the same address\n");
 229             }
 230             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 231                                    writebacks);
 232             ++fastWrites;
 233         }
 234     }
 235     while (!writebacks.empty()) {
 236         missQueue->doWriteback(writebacks.front());
 237         writebacks.pop_front();
 238     }
 239     DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
 240             pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 241             pkt->getAddr() & ~((Addr)blkSize - 1));
 242     if (blk) {
 243         // Hit
 244         hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 245         // clear dirty bit if write through
 246         if (pkt->needsResponse())
 247             respond(pkt, curTick+lat);
 248 //      return MA_HIT;
 249         return true;
 250     }
 251
 252     // Miss
 253     if (!pkt->req->isUncacheable()) {
 254         misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 255         /** @todo Move miss count code into BaseCache */
 256         if (missCount) {
 257             --missCount;
 258             if (missCount == 0)
 259                 exitSimLoop("A cache reached the maximum miss count");
 260         }
 261     }
 262     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 263 //    return MA_CACHE_MISS;
 264     return true;
 265 }
 266
 267
 268 template<class TagStore, class Buffering, class Coherence>
 269 Packet *
 270 Cache<TagStore,Buffering,Coherence>::getPacket()
 271 {
 272     Packet * pkt = missQueue->getPacket();
 273     if (pkt) {
 274         if (!pkt->req->isUncacheable()) {
 275             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
 276             BlkType *blk = tags->findBlock(pkt);
 277             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 278                                               (blk)? blk->status : 0);
 279             missQueue->setBusCmd(pkt, cmd);
 280         }
 281     }
 282
 283     assert(!doMasterRequest() || missQueue->havePending());
 284     assert(!pkt || pkt->time <= curTick);
 285     return pkt;
 286 }
 287
 288 template<class TagStore, class Buffering, class Coherence>
 289 void
 290 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
 291 {
 292     if (success) {
 293               missQueue->markInService(pkt, mshr);
 294           //Temp Hack for UPGRADES
 295           if (pkt->cmd == Packet::UpgradeReq) {
 296               handleResponse(pkt);
 297           }
 298     } else if (pkt && !pkt->req->isUncacheable()) {
 299         missQueue->restoreOrigCmd(pkt);
 300     }
 301 }
 302
 303 template<class TagStore, class Buffering, class Coherence>
 304 void
 305 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 306 {
 307     BlkType *blk = NULL;
 308     if (pkt->senderState) {
 309 //      MemDebug::cacheResponse(pkt);
 310         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 311                 pkt->getAddr() & (((ULL(1))<<48)-1));
 312
 313         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 314             blk = tags->findBlock(pkt);
 315             CacheBlk::State old_state = (blk) ? blk->status : 0;
 316             PacketList writebacks;
 317             CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
 318             DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
 319                     pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
 320             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 321                                    new_state, writebacks, pkt);
 322             while (!writebacks.empty()) {
 323                     missQueue->doWriteback(writebacks.front());
 324                     writebacks.pop_front();
 325             }
 326         }
 327         missQueue->handleResponse(pkt, curTick + hitLatency);
 328     }
 329 }
 330
 331 template<class TagStore, class Buffering, class Coherence>
 332 void
 333 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
 334 {
 335     // Need to temporarily move this blk into MSHRs
 336     MSHR *mshr = missQueue->allocateTargetList(addr);
 337     int lat;
 338     PacketList dummy;
 339     // Read the data into the mshr
 340     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 341     assert(dummy.empty());
 342     assert(mshr->pkt->flags & SATISFIED);
 343     // can overload order since it isn't used on non pending blocks
 344     mshr->order = blk->status;
 345     // temporarily remove the block from the cache.
 346     tags->invalidateBlk(addr);
 347 }
 348
 349 template<class TagStore, class Buffering, class Coherence>
 350 void
 351 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 352 {
 353     // Need to temporarily move this blk into MSHRs
 354     assert(mshr->pkt->cmd == Packet::ReadReq);
 355     int lat;
 356     PacketList dummy;
 357     // Read the data into the mshr
 358     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 359     assert(dummy.empty());
 360     assert(mshr->pkt->flags & SATISFIED);
 361     // can overload order since it isn't used on non pending blocks
 362     mshr->order = blk->status;
 363     // temporarily remove the block from the cache.
 364     tags->invalidateBlk(mshr->pkt->getAddr());
 365 }
 366
 367
 368 template<class TagStore, class Buffering, class Coherence>
 369 Packet *
 370 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
 371 {
 372     return coherence->getPacket();
 373 }
 374
 375
 376 template<class TagStore, class Buffering, class Coherence>
 377 void
 378 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 379 {
 380     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 381     BlkType *blk = tags->findBlock(pkt);
 382     MSHR *mshr = missQueue->findMSHR(blk_addr);
 383     if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
 384         //If we find an mshr, and it is in service, we need to NACK or invalidate
 385         if (mshr) {
 386             if (mshr->inService) {
 387                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 388                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 389                     //If the outstanding request was an invalidate (upgrade,readex,..)
 390                     //Then we need to ACK the request until we get the data
 391                     //Also NACK if the outstanding request is not a cachefill (writeback)
 392                     assert(!(pkt->flags & SATISFIED));
 393                     pkt->flags |= SATISFIED;
 394                     pkt->flags |= NACKED_LINE;
 395                     assert("Don't detect these on the other side yet\n");
 396                     respondToSnoop(pkt, curTick + hitLatency);
 397                     return;
 398                 }
 399                 else {
 400                     //The supplier will be someone else, because we are waiting for
 401                     //the data.  This should cause this cache to be forced to go to
 402                     //the shared state, not the exclusive even though the shared line
 403                     //won't be asserted.  But for now we will just invlidate ourselves
 404                     //and allow the other cache to go into the exclusive state.
 405                     //@todo Make it so a read to a pending read doesn't invalidate.
 406                     //@todo Make it so that a read to a pending read can't be exclusive now.
 407
 408                     //Set the address so find match works
 409                     assert("Don't have invalidates yet\n");
 410                     invalidatePkt->addrOverride(pkt->getAddr());
 411
 412                     //Append the invalidate on
 413                     missQueue->addTarget(mshr,invalidatePkt);
 414                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 415                     return;
 416                 }
 417             }
 418         }
 419         //We also need to check the writeback buffers and handle those
 420         std::vector<MSHR *> writebacks;
 421         if (missQueue->findWrites(blk_addr, writebacks)) {
 422             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 423
 424             //Look through writebacks for any non-uncachable writes, use that
 425             for (int i=0; i<writebacks.size(); i++) {
 426                 mshr = writebacks[i];
 427
 428                 if (!mshr->pkt->req->isUncacheable()) {
 429                     if (pkt->isRead()) {
 430                         //Only Upgrades don't get here
 431                         //Supply the data
 432                         assert(!(pkt->flags & SATISFIED));
 433                         pkt->flags |= SATISFIED;
 434
 435                         //If we are in an exclusive protocol, make it ask again
 436                         //to get write permissions (upgrade), signal shared
 437                         pkt->flags |= SHARED_LINE;
 438
 439                         assert(pkt->isRead());
 440                         Addr offset = pkt->getAddr() & ~(blkSize - 1);
 441                         assert(offset < blkSize);
 442                         assert(pkt->getSize() <= blkSize);
 443                         assert(offset + pkt->getSize() <=blkSize);
 444                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 445
 446                         respondToSnoop(pkt, curTick + hitLatency);
 447                     }
 448
 449                     if (pkt->isInvalidate()) {
 450                         //This must be an upgrade or other cache will take ownership
 451                         missQueue->markInService(mshr->pkt, mshr);
 452                     }
 453                     return;
 454                 }
 455             }
 456         }
 457     }
 458     CacheBlk::State new_state;
 459     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 460     if (satisfy) {
 461         DPRINTF(Cache, "Cache snooped a %s request and now supplying data,"
 462                 "new state is %i\n",
 463                 pkt->cmdString(), new_state);
 464
 465         tags->handleSnoop(blk, new_state, pkt);
 466         respondToSnoop(pkt, curTick + hitLatency);
 467         return;
 468     }
 469     if (blk) DPRINTF(Cache, "Cache snooped a %s request, new state is %i\n",
 470                      pkt->cmdString(), new_state);
 471     tags->handleSnoop(blk, new_state);
 472 }
 473
 474 template<class TagStore, class Buffering, class Coherence>
 475 void
 476 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 477 {
 478     //Need to handle the response, if NACKED
 479     if (pkt->flags & NACKED_LINE) {
 480         //Need to mark it as not in service, and retry for bus
 481         assert(0); //Yeah, we saw a NACK come through
 482
 483         //For now this should never get called, we return false when we see a NACK
 484         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 485         //For now it retrys in just 2 cycles, need to figure out how to change that
 486         //Eventually we will want to also have success come in as a parameter
 487         //Need to make sure that we handle the functionality that happens on successufl
 488         //return of the sendAddr function
 489     }
 490 }
 491
 492 template<class TagStore, class Buffering, class Coherence>
 493 void
 494 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
 495 {
 496     tags->invalidateBlk(addr);
 497 }
 498
 499
 500 /**
 501  * @todo Fix to not assume write allocate
 502  */
 503 template<class TagStore, class Buffering, class Coherence>
 504 Tick
 505 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
 506 {
 507 //    MemDebug::cacheProbe(pkt);
 508     if (!pkt->req->isUncacheable()) {
 509         if (pkt->isInvalidate() && !pkt->isRead()
 510             && !pkt->isWrite()) {
 511             //Upgrade or Invalidate, satisfy it, don't forward
 512             DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
 513                     pkt->getAddr() & (((ULL(1))<<48)-1),
 514                     pkt->getAddr() & ~((Addr)blkSize - 1));
 515             pkt->flags |= SATISFIED;
 516             return 0;
 517         }
 518     }
 519
 520     PacketList writebacks;
 521     int lat;
 522     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 523
 524     if (!blk) {
 525         // Need to check for outstanding misses and writes
 526         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 527
 528         // There can only be one matching outstanding miss.
 529         MSHR* mshr = missQueue->findMSHR(blk_addr);
 530
 531         // There can be many matching outstanding writes.
 532         std::vector<MSHR*> writes;
 533         missQueue->findWrites(blk_addr, writes);
 534
 535         if (!update) {
 536                 otherSidePort->sendFunctional(pkt);
 537
 538             // Check for data in MSHR and writebuffer.
 539             if (mshr) {
 540                 warn("Found outstanding miss on an non-update probe");
 541                 MSHR::TargetList *targets = mshr->getTargetList();
 542                 MSHR::TargetList::iterator i = targets->begin();
 543                 MSHR::TargetList::iterator end = targets->end();
 544                 for (; i != end; ++i) {
 545                     Packet * target = *i;
 546                     // If the target contains data, and it overlaps the
 547                     // probed request, need to update data
 548                     if (target->isWrite() && target->intersect(pkt)) {
 549                         uint8_t* pkt_data;
 550                         uint8_t* write_data;
 551                         int data_size;
 552                         if (target->getAddr() < pkt->getAddr()) {
 553                             int offset = pkt->getAddr() - target->getAddr();
 554                             pkt_data = pkt->getPtr<uint8_t>();
 555                             write_data = target->getPtr<uint8_t>() + offset;
 556                             data_size = target->getSize() - offset;
 557                             assert(data_size > 0);
 558                             if (data_size > pkt->getSize())
 559                                 data_size = pkt->getSize();
 560                         } else {
 561                             int offset = target->getAddr() - pkt->getAddr();
 562                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 563                             write_data = target->getPtr<uint8_t>();
 564                             data_size = pkt->getSize() - offset;
 565                             assert(data_size > pkt->getSize());
 566                             if (data_size > target->getSize())
 567                                 data_size = target->getSize();
 568                         }
 569
 570                         if (pkt->isWrite()) {
 571                             memcpy(pkt_data, write_data, data_size);
 572                         } else {
 573                             memcpy(write_data, pkt_data, data_size);
 574                         }
 575                     }
 576                 }
 577             }
 578             for (int i = 0; i < writes.size(); ++i) {
 579                 Packet * write = writes[i]->pkt;
 580                 if (write->intersect(pkt)) {
 581                     warn("Found outstanding write on an non-update probe");
 582                     uint8_t* pkt_data;
 583                     uint8_t* write_data;
 584                     int data_size;
 585                     if (write->getAddr() < pkt->getAddr()) {
 586                         int offset = pkt->getAddr() - write->getAddr();
 587                         pkt_data = pkt->getPtr<uint8_t>();
 588                         write_data = write->getPtr<uint8_t>() + offset;
 589                         data_size = write->getSize() - offset;
 590                         assert(data_size > 0);
 591                         if (data_size > pkt->getSize())
 592                             data_size = pkt->getSize();
 593                     } else {
 594                         int offset = write->getAddr() - pkt->getAddr();
 595                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 596                         write_data = write->getPtr<uint8_t>();
 597                         data_size = pkt->getSize() - offset;
 598                         assert(data_size > pkt->getSize());
 599                         if (data_size > write->getSize())
 600                             data_size = write->getSize();
 601                     }
 602
 603                     if (pkt->isWrite()) {
 604                         memcpy(pkt_data, write_data, data_size);
 605                     } else {
 606                         memcpy(write_data, pkt_data, data_size);
 607                     }
 608
 609                 }
 610             }
 611             return 0;
 612         } else {
 613             // update the cache state and statistics
 614             if (mshr || !writes.empty()){
 615                 // Can't handle it, return pktuest unsatisfied.
 616                 panic("Atomic access ran into outstanding MSHR's or WB's!");
 617             }
 618             if (!pkt->req->isUncacheable()) {
 619                 // Fetch the cache block to fill
 620                 BlkType *blk = tags->findBlock(pkt);
 621                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 622                                                    (blk)? blk->status : 0);
 623
 624                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 625
 626                 busPkt->allocate();
 627
 628                 busPkt->time = curTick;
 629
 630                 lat = memSidePort->sendAtomic(busPkt);
 631
 632                 //Be sure to flip the response to a request for coherence
 633                 if (busPkt->needsResponse()) {
 634                     busPkt->makeAtomicResponse();
 635                 }
 636
 637 /*              if (!(busPkt->flags & SATISFIED)) {
 638                     // blocked at a higher level, just return
 639                     return 0;
 640                 }
 641
 642 */              misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 643
 644                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 645                 tags->handleFill(blk, busPkt,
 646                                  coherence->getNewState(busPkt, old_state),
 647                                  writebacks, pkt);
 648                 // Handle writebacks if needed
 649                 while (!writebacks.empty()){
 650                     memSidePort->sendAtomic(writebacks.front());
 651                     writebacks.pop_front();
 652                 }
 653                 return lat + hitLatency;
 654             } else {
 655                 return memSidePort->sendAtomic(pkt);
 656             }
 657         }
 658     } else {
 659         // There was a cache hit.
 660         // Handle writebacks if needed
 661         while (!writebacks.empty()){
 662             memSidePort->sendAtomic(writebacks.front());
 663             writebacks.pop_front();
 664         }
 665
 666         if (update) {
 667             hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
 668         } else if (pkt->isWrite()) {
 669             // Still need to change data in all locations.
 670             otherSidePort->sendFunctional(pkt);
 671         }
 672         return curTick + lat;
 673     }
 674     fatal("Probe not handled.\n");
 675     return 0;
 676 }
 677
 678 template<class TagStore, class Buffering, class Coherence>
 679 Tick
 680 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
 681 {
 682         Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 683         BlkType *blk = tags->findBlock(pkt);
 684         MSHR *mshr = missQueue->findMSHR(blk_addr);
 685         CacheBlk::State new_state = 0;
 686         bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 687         if (satisfy) {
 688             DPRINTF(Cache, "Cache snooped a %s request and now supplying data,"
 689                     "new state is %i\n",
 690                     pkt->cmdString(), new_state);
 691
 692             tags->handleSnoop(blk, new_state, pkt);
 693             return hitLatency;
 694         }
 695         if (blk) DPRINTF(Cache, "Cache snooped a %s request, new state is %i\n",
 696                      pkt->cmdString(), new_state);
 697         tags->handleSnoop(blk, new_state);
 698         return 0;
 699 }
 700