2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Erik Hallnor
45 #include "sim/host.hh"
46 #include "base/misc.hh"
49 #include "mem/cache/cache.hh"
50 #include "mem/cache/cache_blk.hh"
51 #include "mem/cache/miss/mshr.hh"
52 #include "mem/cache/prefetch/prefetcher.hh"
54 #include "sim/sim_exit.hh" // for SimExitEvent
56 template<class TagStore, class Buffering, class Coherence>
58 Cache<TagStore,Buffering,Coherence>::
59 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
63 if (pkt->isWrite() && (pkt->req->isLocked())) {
64 pkt->req->setScResult(1);
71 if (pkt->isResponse())
74 //Check if we should do the snoop
75 if (pkt->flags & SNOOP_COMMIT)
82 template<class TagStore, class Buffering, class Coherence>
84 Cache<TagStore,Buffering,Coherence>::
85 doAtomicAccess(Packet *pkt, bool isCpuSide)
89 //Temporary solution to LL/SC
90 if (pkt->isWrite() && (pkt->req->isLocked())) {
91 pkt->req->setScResult(1);
94 probe(pkt, true, NULL);
95 //TEMP ALWAYS SUCCES FOR NOW
96 pkt->result = Packet::Success;
100 if (pkt->isResponse())
105 //Fix this timing info
109 template<class TagStore, class Buffering, class Coherence>
111 Cache<TagStore,Buffering,Coherence>::
112 doFunctionalAccess(Packet *pkt, bool isCpuSide)
116 //TEMP USE CPU?THREAD 0 0
117 pkt->req->setThreadContext(0,0);
119 //Temporary solution to LL/SC
120 if (pkt->isWrite() && (pkt->req->isLocked())) {
121 assert("Can't handle LL/SC on functional path\n");
124 probe(pkt, false, memSidePort);
125 //TEMP ALWAYS SUCCESFUL FOR NOW
126 pkt->result = Packet::Success;
130 probe(pkt, false, cpuSidePort);
134 template<class TagStore, class Buffering, class Coherence>
136 Cache<TagStore,Buffering,Coherence>::
137 recvStatusChange(Port::Status status, bool isCpuSide)
143 template<class TagStore, class Buffering, class Coherence>
144 Cache<TagStore,Buffering,Coherence>::
145 Cache(const std::string &_name,
146 Cache<TagStore,Buffering,Coherence>::Params ¶ms)
147 : BaseCache(_name, params.baseParams),
148 prefetchAccess(params.prefetchAccess),
149 tags(params.tags), missQueue(params.missQueue),
150 coherence(params.coherence), prefetcher(params.prefetcher),
151 doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
154 // if (params.in == NULL) {
155 topLevelCache = true;
157 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
158 tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
159 tags->setPrefetcher(prefetcher);
160 missQueue->setCache(this);
161 missQueue->setPrefetcher(prefetcher);
162 coherence->setCache(this);
163 prefetcher->setCache(this);
164 prefetcher->setTags(tags);
165 prefetcher->setBuffer(missQueue);
166 invalidateReq = new Request((Addr) NULL, blkSize, 0);
167 invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
170 template<class TagStore, class Buffering, class Coherence>
172 Cache<TagStore,Buffering,Coherence>::regStats()
174 BaseCache::regStats();
175 tags->regStats(name());
176 missQueue->regStats(name());
177 coherence->regStats(name());
178 prefetcher->regStats(name());
181 template<class TagStore, class Buffering, class Coherence>
183 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
185 //@todo Add back in MemDebug Calls
186 // MemDebug::cacheAccess(pkt);
188 PacketList writebacks;
190 int lat = hitLatency;
191 if (prefetchAccess) {
192 //We are determining prefetches on access stream, call prefetcher
193 prefetcher->handleMiss(pkt, curTick);
195 if (!pkt->req->isUncacheable()) {
196 if (pkt->isInvalidate() && !pkt->isRead()
197 && !pkt->isWrite()) {
198 //Upgrade or Invalidate
199 //Look into what happens if two slave caches on bus
200 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
201 pkt->getAddr() & (((ULL(1))<<48)-1),
202 pkt->getAddr() & ~((Addr)blkSize - 1));
204 pkt->flags |= SATISFIED;
205 //Invalidates/Upgrades need no response if they get the bus
206 // return MA_HIT; //@todo, return values
209 blk = tags->handleAccess(pkt, lat, writebacks);
211 size = pkt->getSize();
213 // If this is a block size write/hint (WH64) allocate the block here
214 // if the coherence protocol allows it.
215 /** @todo make the fast write alloc (wh64) work with coherence. */
216 /** @todo Do we want to do fast writes for writebacks as well? */
217 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
218 (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
219 // not outstanding misses, can do this
220 MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
221 if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
222 if (outstanding_miss) {
223 warn("WriteInv doing a fastallocate"
224 "with an outstanding miss to the same address\n");
226 blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
231 while (!writebacks.empty()) {
232 missQueue->doWriteback(writebacks.front());
233 writebacks.pop_front();
235 DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
236 pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
237 pkt->getAddr() & ~((Addr)blkSize - 1));
240 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
241 // clear dirty bit if write through
242 if (pkt->needsResponse())
243 respond(pkt, curTick+lat);
249 if (!pkt->req->isUncacheable()) {
250 misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
251 /** @todo Move miss count code into BaseCache */
255 exitSimLoop("A cache reached the maximum miss count");
258 missQueue->handleMiss(pkt, size, curTick + hitLatency);
259 // return MA_CACHE_MISS;
264 template<class TagStore, class Buffering, class Coherence>
266 Cache<TagStore,Buffering,Coherence>::getPacket()
268 assert(missQueue->havePending());
269 Packet * pkt = missQueue->getPacket();
271 if (!pkt->req->isUncacheable()) {
272 if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
273 BlkType *blk = tags->findBlock(pkt);
274 Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
275 (blk)? blk->status : 0);
276 missQueue->setBusCmd(pkt, cmd);
280 assert(!doMasterRequest() || missQueue->havePending());
281 assert(!pkt || pkt->time <= curTick);
285 template<class TagStore, class Buffering, class Coherence>
287 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
289 if (success && !(pkt->flags & NACKED_LINE)) {
290 missQueue->markInService(pkt, mshr);
291 //Temp Hack for UPGRADES
292 if (pkt->cmd == Packet::UpgradeReq) {
293 pkt->flags &= ~CACHE_LINE_FILL;
294 BlkType *blk = tags->findBlock(pkt);
295 CacheBlk::State old_state = (blk) ? blk->status : 0;
296 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
297 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
298 pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
299 //Set the state on the upgrade
300 memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
301 PacketList writebacks;
302 tags->handleFill(blk, mshr, new_state, writebacks, pkt);
303 assert(writebacks.empty());
304 missQueue->handleResponse(pkt, curTick + hitLatency);
306 } else if (pkt && !pkt->req->isUncacheable()) {
307 pkt->flags &= ~NACKED_LINE;
308 pkt->flags &= ~SATISFIED;
309 pkt->flags &= ~SNOOP_COMMIT;
310 missQueue->restoreOrigCmd(pkt);
314 template<class TagStore, class Buffering, class Coherence>
316 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
319 if (pkt->senderState) {
320 if (pkt->result == Packet::Nacked) {
321 //pkt->reinitFromRequest();
322 warn("NACKs from devices not connected to the same bus not implemented\n");
325 if (pkt->result == Packet::BadAddress) {
326 //Make the response a Bad address and send it
328 // MemDebug::cacheResponse(pkt);
329 DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
330 pkt->getAddr() & (((ULL(1))<<48)-1));
332 if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
333 blk = tags->findBlock(pkt);
334 CacheBlk::State old_state = (blk) ? blk->status : 0;
335 PacketList writebacks;
336 CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
337 DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
338 pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
339 blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
340 new_state, writebacks, pkt);
341 while (!writebacks.empty()) {
342 missQueue->doWriteback(writebacks.front());
343 writebacks.pop_front();
346 missQueue->handleResponse(pkt, curTick + hitLatency);
350 template<class TagStore, class Buffering, class Coherence>
352 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
354 // Need to temporarily move this blk into MSHRs
355 MSHR *mshr = missQueue->allocateTargetList(addr);
358 // Read the data into the mshr
359 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
360 assert(dummy.empty());
361 assert(mshr->pkt->flags & SATISFIED);
362 // can overload order since it isn't used on non pending blocks
363 mshr->order = blk->status;
364 // temporarily remove the block from the cache.
365 tags->invalidateBlk(addr);
368 template<class TagStore, class Buffering, class Coherence>
370 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
372 // Need to temporarily move this blk into MSHRs
373 assert(mshr->pkt->cmd == Packet::ReadReq);
376 // Read the data into the mshr
377 BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
378 assert(dummy.empty());
379 assert(mshr->pkt->flags & SATISFIED);
380 // can overload order since it isn't used on non pending blocks
381 mshr->order = blk->status;
382 // temporarily remove the block from the cache.
383 tags->invalidateBlk(mshr->pkt->getAddr());
387 template<class TagStore, class Buffering, class Coherence>
389 Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
391 return coherence->getPacket();
395 template<class TagStore, class Buffering, class Coherence>
397 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
399 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
400 BlkType *blk = tags->findBlock(pkt);
401 MSHR *mshr = missQueue->findMSHR(blk_addr);
402 if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
403 //If we find an mshr, and it is in service, we need to NACK or invalidate
405 if (mshr->inService) {
406 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
407 && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
408 //If the outstanding request was an invalidate (upgrade,readex,..)
409 //Then we need to ACK the request until we get the data
410 //Also NACK if the outstanding request is not a cachefill (writeback)
411 assert(!(pkt->flags & SATISFIED));
412 pkt->flags |= SATISFIED;
413 pkt->flags |= NACKED_LINE;
414 ///@todo NACK's from other levels
415 //warn("NACKs from devices not connected to the same bus not implemented\n");
416 //respondToSnoop(pkt, curTick + hitLatency);
420 //The supplier will be someone else, because we are waiting for
421 //the data. This should cause this cache to be forced to go to
422 //the shared state, not the exclusive even though the shared line
423 //won't be asserted. But for now we will just invlidate ourselves
424 //and allow the other cache to go into the exclusive state.
425 //@todo Make it so a read to a pending read doesn't invalidate.
426 //@todo Make it so that a read to a pending read can't be exclusive now.
428 //Set the address so find match works
429 //panic("Don't have invalidates yet\n");
430 invalidatePkt->addrOverride(pkt->getAddr());
432 //Append the invalidate on
433 missQueue->addTarget(mshr,invalidatePkt);
434 DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
439 //We also need to check the writeback buffers and handle those
440 std::vector<MSHR *> writebacks;
441 if (missQueue->findWrites(blk_addr, writebacks)) {
442 DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
444 //Look through writebacks for any non-uncachable writes, use that
445 for (int i=0; i<writebacks.size(); i++) {
446 mshr = writebacks[i];
448 if (!mshr->pkt->req->isUncacheable()) {
450 //Only Upgrades don't get here
452 assert(!(pkt->flags & SATISFIED));
453 pkt->flags |= SATISFIED;
455 //If we are in an exclusive protocol, make it ask again
456 //to get write permissions (upgrade), signal shared
457 pkt->flags |= SHARED_LINE;
459 assert(pkt->isRead());
460 Addr offset = pkt->getAddr() & (blkSize - 1);
461 assert(offset < blkSize);
462 assert(pkt->getSize() <= blkSize);
463 assert(offset + pkt->getSize() <=blkSize);
464 memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
466 respondToSnoop(pkt, curTick + hitLatency);
469 if (pkt->isInvalidate()) {
470 //This must be an upgrade or other cache will take ownership
471 missQueue->markInService(mshr->pkt, mshr);
478 CacheBlk::State new_state;
479 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
481 DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
483 pkt->cmdString(), blk_addr, new_state);
485 tags->handleSnoop(blk, new_state, pkt);
486 respondToSnoop(pkt, curTick + hitLatency);
489 if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
490 pkt->cmdString(), blk_addr, new_state);
491 tags->handleSnoop(blk, new_state);
494 template<class TagStore, class Buffering, class Coherence>
496 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
498 //Need to handle the response, if NACKED
499 if (pkt->flags & NACKED_LINE) {
500 //Need to mark it as not in service, and retry for bus
501 assert(0); //Yeah, we saw a NACK come through
503 //For now this should never get called, we return false when we see a NACK
504 //instead, by doing this we allow the bus_blocked mechanism to handle the retry
505 //For now it retrys in just 2 cycles, need to figure out how to change that
506 //Eventually we will want to also have success come in as a parameter
507 //Need to make sure that we handle the functionality that happens on successufl
508 //return of the sendAddr function
512 template<class TagStore, class Buffering, class Coherence>
514 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
516 tags->invalidateBlk(addr);
521 * @todo Fix to not assume write allocate
523 template<class TagStore, class Buffering, class Coherence>
525 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
527 // MemDebug::cacheProbe(pkt);
528 if (!pkt->req->isUncacheable()) {
529 if (pkt->isInvalidate() && !pkt->isRead()
530 && !pkt->isWrite()) {
531 //Upgrade or Invalidate, satisfy it, don't forward
532 DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
533 pkt->getAddr() & (((ULL(1))<<48)-1),
534 pkt->getAddr() & ~((Addr)blkSize - 1));
535 pkt->flags |= SATISFIED;
540 PacketList writebacks;
542 BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
545 // Need to check for outstanding misses and writes
546 Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
548 // There can only be one matching outstanding miss.
549 MSHR* mshr = missQueue->findMSHR(blk_addr);
551 // There can be many matching outstanding writes.
552 std::vector<MSHR*> writes;
553 missQueue->findWrites(blk_addr, writes);
556 otherSidePort->sendFunctional(pkt);
558 // Check for data in MSHR and writebuffer.
560 warn("Found outstanding miss on an non-update probe");
561 MSHR::TargetList *targets = mshr->getTargetList();
562 MSHR::TargetList::iterator i = targets->begin();
563 MSHR::TargetList::iterator end = targets->end();
564 for (; i != end; ++i) {
565 Packet * target = *i;
566 // If the target contains data, and it overlaps the
567 // probed request, need to update data
568 if (target->isWrite() && target->intersect(pkt)) {
572 if (target->getAddr() < pkt->getAddr()) {
573 int offset = pkt->getAddr() - target->getAddr();
574 pkt_data = pkt->getPtr<uint8_t>();
575 write_data = target->getPtr<uint8_t>() + offset;
576 data_size = target->getSize() - offset;
577 assert(data_size > 0);
578 if (data_size > pkt->getSize())
579 data_size = pkt->getSize();
581 int offset = target->getAddr() - pkt->getAddr();
582 pkt_data = pkt->getPtr<uint8_t>() + offset;
583 write_data = target->getPtr<uint8_t>();
584 data_size = pkt->getSize() - offset;
585 assert(data_size > pkt->getSize());
586 if (data_size > target->getSize())
587 data_size = target->getSize();
590 if (pkt->isWrite()) {
591 memcpy(pkt_data, write_data, data_size);
593 memcpy(write_data, pkt_data, data_size);
598 for (int i = 0; i < writes.size(); ++i) {
599 Packet * write = writes[i]->pkt;
600 if (write->intersect(pkt)) {
601 warn("Found outstanding write on an non-update probe");
605 if (write->getAddr() < pkt->getAddr()) {
606 int offset = pkt->getAddr() - write->getAddr();
607 pkt_data = pkt->getPtr<uint8_t>();
608 write_data = write->getPtr<uint8_t>() + offset;
609 data_size = write->getSize() - offset;
610 assert(data_size > 0);
611 if (data_size > pkt->getSize())
612 data_size = pkt->getSize();
614 int offset = write->getAddr() - pkt->getAddr();
615 pkt_data = pkt->getPtr<uint8_t>() + offset;
616 write_data = write->getPtr<uint8_t>();
617 data_size = pkt->getSize() - offset;
618 assert(data_size > pkt->getSize());
619 if (data_size > write->getSize())
620 data_size = write->getSize();
623 if (pkt->isWrite()) {
624 memcpy(pkt_data, write_data, data_size);
626 memcpy(write_data, pkt_data, data_size);
633 // update the cache state and statistics
634 if (mshr || !writes.empty()){
635 // Can't handle it, return pktuest unsatisfied.
636 panic("Atomic access ran into outstanding MSHR's or WB's!");
638 if (!pkt->req->isUncacheable()) {
639 // Fetch the cache block to fill
640 BlkType *blk = tags->findBlock(pkt);
641 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
642 (blk)? blk->status : 0);
644 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
648 busPkt->time = curTick;
650 lat = memSidePort->sendAtomic(busPkt);
652 //Be sure to flip the response to a request for coherence
653 if (busPkt->needsResponse()) {
654 busPkt->makeAtomicResponse();
657 /* if (!(busPkt->flags & SATISFIED)) {
658 // blocked at a higher level, just return
662 */ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
664 CacheBlk::State old_state = (blk) ? blk->status : 0;
665 tags->handleFill(blk, busPkt,
666 coherence->getNewState(busPkt, old_state),
668 // Handle writebacks if needed
669 while (!writebacks.empty()){
670 memSidePort->sendAtomic(writebacks.front());
671 writebacks.pop_front();
673 return lat + hitLatency;
675 return memSidePort->sendAtomic(pkt);
679 // There was a cache hit.
680 // Handle writebacks if needed
681 while (!writebacks.empty()){
682 memSidePort->sendAtomic(writebacks.front());
683 writebacks.pop_front();
687 hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
688 } else if (pkt->isWrite()) {
689 // Still need to change data in all locations.
690 otherSidePort->sendFunctional(pkt);
692 return curTick + lat;
694 fatal("Probe not handled.\n");
698 template<class TagStore, class Buffering, class Coherence>
700 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
702 Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
703 BlkType *blk = tags->findBlock(pkt);
704 MSHR *mshr = missQueue->findMSHR(blk_addr);
705 CacheBlk::State new_state = 0;
706 bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
708 DPRINTF(Cache, "Cache snooped a %s request for addr %x and now supplying data,"
710 pkt->cmdString(), blk_addr, new_state);
712 tags->handleSnoop(blk, new_state, pkt);
715 if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, new state is %i\n",
716 pkt->cmdString(), blk_addr, new_state);
717 tags->handleSnoop(blk, new_state);