src/mem/cache/cache_impl.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 /**
  34  * @file
  35  * Cache definitions.
  36  */
  37
  38 #include <assert.h>
  39 #include <math.h>
  40
  41 #include <cassert>
  42 #include <iostream>
  43 #include <string>
  44
  45 #include "sim/host.hh"
  46 #include "base/misc.hh"
  47 #include "cpu/smt.hh"
  48
  49 #include "mem/cache/cache.hh"
  50 #include "mem/cache/cache_blk.hh"
  51 #include "mem/cache/miss/mshr.hh"
  52 #include "mem/cache/prefetch/prefetcher.hh"
  53
  54 #include "sim/sim_events.hh" // for SimExitEvent
  55
  56 using namespace std;
  57
  58 template<class TagStore, class Buffering, class Coherence>
  59 bool
  60 Cache<TagStore,Buffering,Coherence>::
  61 doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  62 {
  63     if (isCpuSide)
  64     {
  65         access(pkt);
  66     }
  67     else
  68     {
  69         if (pkt->isResponse())
  70             handleResponse(pkt);
  71         else
  72             snoop(pkt);
  73     }
  74     return true; //Deal with blocking....
  75 }
  76
  77 template<class TagStore, class Buffering, class Coherence>
  78 Tick
  79 Cache<TagStore,Buffering,Coherence>::
  80 doAtomicAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
  81 {
  82     if (isCpuSide)
  83     {
  84         probe(pkt, true);
  85     }
  86     else
  87     {
  88         if (pkt->isResponse())
  89             handleResponse(pkt);
  90         else
  91             snoopProbe(pkt, true);
  92     }
  93     //Fix this timing info
  94     return hitLatency;
  95 }
  96
  97 template<class TagStore, class Buffering, class Coherence>
  98 void
  99 Cache<TagStore,Buffering,Coherence>::
 100 doFunctionalAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 101 {
 102     if (isCpuSide)
 103     {
 104         probe(pkt, false);
 105     }
 106     else
 107     {
 108         if (pkt->isResponse())
 109             handleResponse(pkt);
 110         else
 111             snoopProbe(pkt, false);
 112     }
 113 }
 114
 115 template<class TagStore, class Buffering, class Coherence>
 116 void
 117 Cache<TagStore,Buffering,Coherence>::
 118 recvStatusChange(Port::Status status, bool isCpuSide)
 119 {
 120
 121 }
 122
 123
 124 template<class TagStore, class Buffering, class Coherence>
 125 Cache<TagStore,Buffering,Coherence>::
 126 Cache(const std::string &_name,
 127       Cache<TagStore,Buffering,Coherence>::Params &params)
 128     : BaseCache(_name, params.baseParams),
 129       prefetchAccess(params.prefetchAccess),
 130       tags(params.tags), missQueue(params.missQueue),
 131       coherence(params.coherence), prefetcher(params.prefetcher),
 132       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
 133 {
 134 //FIX BUS POINTERS
 135 //    if (params.in == NULL) {
 136         topLevelCache = true;
 137 //    }
 138 //PLEASE FIX THIS, BUS SIZES NOT BEING USED
 139         tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
 140     tags->setPrefetcher(prefetcher);
 141     missQueue->setCache(this);
 142     missQueue->setPrefetcher(prefetcher);
 143     coherence->setCache(this);
 144     prefetcher->setCache(this);
 145     prefetcher->setTags(tags);
 146     prefetcher->setBuffer(missQueue);
 147 #if 0
 148     invalidatePkt = new Packet;
 149     invalidatePkt->cmd = Packet::InvalidateReq;
 150 #endif
 151 }
 152
 153 template<class TagStore, class Buffering, class Coherence>
 154 void
 155 Cache<TagStore,Buffering,Coherence>::regStats()
 156 {
 157     BaseCache::regStats();
 158     tags->regStats(name());
 159     missQueue->regStats(name());
 160     coherence->regStats(name());
 161     prefetcher->regStats(name());
 162 }
 163
 164 template<class TagStore, class Buffering, class Coherence>
 165 bool
 166 Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 167 {
 168 //@todo Add back in MemDebug Calls
 169 //    MemDebug::cacheAccess(pkt);
 170     BlkType *blk = NULL;
 171     PacketList writebacks;
 172     int size = blkSize;
 173     int lat = hitLatency;
 174     if (prefetchAccess) {
 175         //We are determining prefetches on access stream, call prefetcher
 176         prefetcher->handleMiss(pkt, curTick);
 177     }
 178     if (!pkt->req->isUncacheable()) {
 179         if (pkt->isInvalidate() && !pkt->isRead()
 180             && !pkt->isWrite()) {
 181             //Upgrade or Invalidate
 182             //Look into what happens if two slave caches on bus
 183             DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
 184                     pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1),
 185                     pkt->getAddr() & ~((Addr)blkSize - 1));
 186
 187             //@todo Should this return latency have the hit latency in it?
 188 //          respond(pkt,curTick+lat);
 189             pkt->flags |= SATISFIED;
 190 //            return MA_HIT; //@todo, return values
 191             return true;
 192         }
 193         blk = tags->handleAccess(pkt, lat, writebacks);
 194     } else {
 195         size = pkt->getSize();
 196     }
 197     // If this is a block size write/hint (WH64) allocate the block here
 198     // if the coherence protocol allows it.
 199     /** @todo make the fast write alloc (wh64) work with coherence. */
 200     /** @todo Do we want to do fast writes for writebacks as well? */
 201     if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
 202         (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
 203         // not outstanding misses, can do this
 204         MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr(), pkt->req->getAsid());
 205         if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
 206             if (outstanding_miss) {
 207                 warn("WriteInv doing a fastallocate"
 208                      "with an outstanding miss to the same address\n");
 209             }
 210             blk = tags->handleFill(NULL, pkt, BlkValid | BlkWritable,
 211                                    writebacks);
 212             ++fastWrites;
 213         }
 214     }
 215     while (!writebacks.empty()) {
 216         missQueue->doWriteback(writebacks.front());
 217         writebacks.pop_front();
 218     }
 219     DPRINTF(Cache, "%s %d %x %s blk_addr: %x pc %x\n", pkt->cmdString(),
 220             pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
 221             pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC());
 222     if (blk) {
 223         // Hit
 224         hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 225         // clear dirty bit if write through
 226         if (pkt->needsResponse())
 227             respond(pkt, curTick+lat);
 228 //      return MA_HIT;
 229         return true;
 230     }
 231
 232     // Miss
 233     if (!pkt->req->isUncacheable()) {
 234         misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 235         /** @todo Move miss count code into BaseCache */
 236         if (missCount) {
 237             --missCount;
 238             if (missCount == 0)
 239                 new SimLoopExitEvent(curTick, "A cache reached the maximum miss count");
 240         }
 241     }
 242     missQueue->handleMiss(pkt, size, curTick + hitLatency);
 243 //    return MA_CACHE_MISS;
 244     return true;
 245 }
 246
 247
 248 template<class TagStore, class Buffering, class Coherence>
 249 Packet *
 250 Cache<TagStore,Buffering,Coherence>::getPacket()
 251 {
 252     Packet * pkt = missQueue->getPacket();
 253     if (pkt) {
 254         if (!pkt->req->isUncacheable()) {
 255             if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][pkt->req->getThreadNum()]++;
 256             BlkType *blk = tags->findBlock(pkt);
 257             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
 258                                               (blk)? blk->status : 0);
 259             missQueue->setBusCmd(pkt, cmd);
 260         }
 261     }
 262
 263     assert(!doMasterRequest() || missQueue->havePending());
 264     assert(!pkt || pkt->time <= curTick);
 265     return pkt;
 266 }
 267
 268 template<class TagStore, class Buffering, class Coherence>
 269 void
 270 Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, bool success)
 271 {
 272     if (success) {
 273         missQueue->markInService(pkt);
 274           //Temp Hack for UPGRADES
 275           if (pkt->cmd == Packet::UpgradeReq) {
 276               handleResponse(pkt);
 277           }
 278     } else if (pkt && !pkt->req->isUncacheable()) {
 279         missQueue->restoreOrigCmd(pkt);
 280     }
 281 }
 282
 283 template<class TagStore, class Buffering, class Coherence>
 284 void
 285 Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 286 {
 287     BlkType *blk = NULL;
 288     if (pkt->senderState) {
 289 //      MemDebug::cacheResponse(pkt);
 290         DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
 291                 pkt->getAddr() & (((ULL(1))<<48)-1));
 292
 293         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
 294             blk = tags->findBlock(pkt);
 295             CacheBlk::State old_state = (blk) ? blk->status : 0;
 296             PacketList writebacks;
 297             blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
 298                                    coherence->getNewState(pkt,old_state),
 299                                    writebacks);
 300             while (!writebacks.empty()) {
 301                     missQueue->doWriteback(writebacks.front());
 302             }
 303         }
 304         missQueue->handleResponse(pkt, curTick + hitLatency);
 305     }
 306 }
 307
 308 template<class TagStore, class Buffering, class Coherence>
 309 void
 310 Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr, int asid)
 311 {
 312     // Need to temporarily move this blk into MSHRs
 313     MSHR *mshr = missQueue->allocateTargetList(addr, asid);
 314     int lat;
 315     PacketList dummy;
 316     // Read the data into the mshr
 317     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 318     assert(dummy.empty());
 319     assert(mshr->pkt->flags & SATISFIED);
 320     // can overload order since it isn't used on non pending blocks
 321     mshr->order = blk->status;
 322     // temporarily remove the block from the cache.
 323     tags->invalidateBlk(addr, asid);
 324 }
 325
 326 template<class TagStore, class Buffering, class Coherence>
 327 void
 328 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 329 {
 330     // Need to temporarily move this blk into MSHRs
 331     assert(mshr->pkt->cmd == Packet::ReadReq);
 332     int lat;
 333     PacketList dummy;
 334     // Read the data into the mshr
 335     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
 336     assert(dummy.empty());
 337     assert(mshr->pkt->flags & SATISFIED);
 338     // can overload order since it isn't used on non pending blocks
 339     mshr->order = blk->status;
 340     // temporarily remove the block from the cache.
 341     tags->invalidateBlk(mshr->pkt->getAddr(), mshr->pkt->req->getAsid());
 342 }
 343
 344
 345 template<class TagStore, class Buffering, class Coherence>
 346 Packet *
 347 Cache<TagStore,Buffering,Coherence>::getCoherenceReq()
 348 {
 349     return coherence->getPacket();
 350 }
 351
 352
 353 template<class TagStore, class Buffering, class Coherence>
 354 void
 355 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 356 {
 357
 358     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 359     BlkType *blk = tags->findBlock(pkt);
 360     MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
 361     if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
 362         //If we find an mshr, and it is in service, we need to NACK or invalidate
 363         if (mshr) {
 364             if (mshr->inService) {
 365                 if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
 366                     && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
 367                     //If the outstanding request was an invalidate (upgrade,readex,..)
 368                     //Then we need to ACK the request until we get the data
 369                     //Also NACK if the outstanding request is not a cachefill (writeback)
 370                     pkt->flags |= NACKED_LINE;
 371                     return;
 372                 }
 373                 else {
 374                     //The supplier will be someone else, because we are waiting for
 375                     //the data.  This should cause this cache to be forced to go to
 376                     //the shared state, not the exclusive even though the shared line
 377                     //won't be asserted.  But for now we will just invlidate ourselves
 378                     //and allow the other cache to go into the exclusive state.
 379                     //@todo Make it so a read to a pending read doesn't invalidate.
 380                     //@todo Make it so that a read to a pending read can't be exclusive now.
 381
 382                     //Set the address so find match works
 383                     invalidatePkt->addrOverride(pkt->getAddr());
 384
 385                     //Append the invalidate on
 386                     missQueue->addTarget(mshr,invalidatePkt);
 387                     DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 388                     return;
 389                 }
 390             }
 391         }
 392         //We also need to check the writeback buffers and handle those
 393         std::vector<MSHR *> writebacks;
 394         if (missQueue->findWrites(blk_addr, pkt->req->getAsid(), writebacks)) {
 395             DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->getAddr() & (((ULL(1))<<48)-1));
 396
 397             //Look through writebacks for any non-uncachable writes, use that
 398             for (int i=0; i<writebacks.size(); i++) {
 399                 mshr = writebacks[i];
 400
 401                 if (!mshr->pkt->req->isUncacheable()) {
 402                     if (pkt->isRead()) {
 403                         //Only Upgrades don't get here
 404                         //Supply the data
 405                         pkt->flags |= SATISFIED;
 406
 407                         //If we are in an exclusive protocol, make it ask again
 408                         //to get write permissions (upgrade), signal shared
 409                         pkt->flags |= SHARED_LINE;
 410
 411                         assert(pkt->isRead());
 412                         Addr offset = pkt->getAddr() & ~(blkSize - 1);
 413                         assert(offset < blkSize);
 414                         assert(pkt->getSize() <= blkSize);
 415                         assert(offset + pkt->getSize() <=blkSize);
 416                         memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
 417
 418                         respondToSnoop(pkt);
 419                     }
 420
 421                     if (pkt->isInvalidate()) {
 422                         //This must be an upgrade or other cache will take ownership
 423                         missQueue->markInService(mshr->pkt);
 424                     }
 425                     return;
 426                 }
 427             }
 428         }
 429     }
 430     CacheBlk::State new_state;
 431     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 432     if (satisfy) {
 433         tags->handleSnoop(blk, new_state, pkt);
 434         respondToSnoop(pkt);
 435         return;
 436     }
 437     tags->handleSnoop(blk, new_state);
 438 }
 439
 440 template<class TagStore, class Buffering, class Coherence>
 441 void
 442 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 443 {
 444     //Need to handle the response, if NACKED
 445     if (pkt->flags & NACKED_LINE) {
 446         //Need to mark it as not in service, and retry for bus
 447         assert(0); //Yeah, we saw a NACK come through
 448
 449         //For now this should never get called, we return false when we see a NACK
 450         //instead, by doing this we allow the bus_blocked mechanism to handle the retry
 451         //For now it retrys in just 2 cycles, need to figure out how to change that
 452         //Eventually we will want to also have success come in as a parameter
 453         //Need to make sure that we handle the functionality that happens on successufl
 454         //return of the sendAddr function
 455     }
 456 }
 457
 458 template<class TagStore, class Buffering, class Coherence>
 459 void
 460 Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr, int asid)
 461 {
 462     tags->invalidateBlk(addr,asid);
 463 }
 464
 465
 466 /**
 467  * @todo Fix to not assume write allocate
 468  */
 469 template<class TagStore, class Buffering, class Coherence>
 470 Tick
 471 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
 472 {
 473 //    MemDebug::cacheProbe(pkt);
 474     if (!pkt->req->isUncacheable()) {
 475         if (pkt->isInvalidate() && !pkt->isRead()
 476             && !pkt->isWrite()) {
 477             //Upgrade or Invalidate, satisfy it, don't forward
 478             DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
 479                     pkt->req->getAsid(), pkt->getAddr() & (((ULL(1))<<48)-1),
 480                     pkt->getAddr() & ~((Addr)blkSize - 1));
 481             pkt->flags |= SATISFIED;
 482             return 0;
 483         }
 484     }
 485
 486     PacketList writebacks;
 487     int lat;
 488     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 489
 490     if (!blk) {
 491         // Need to check for outstanding misses and writes
 492         Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
 493
 494         // There can only be one matching outstanding miss.
 495         MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
 496
 497         // There can be many matching outstanding writes.
 498         vector<MSHR*> writes;
 499         missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
 500
 501         if (!update) {
 502             memSidePort->sendFunctional(pkt);
 503             // Check for data in MSHR and writebuffer.
 504             if (mshr) {
 505                 warn("Found outstanding miss on an non-update probe");
 506                 MSHR::TargetList *targets = mshr->getTargetList();
 507                 MSHR::TargetList::iterator i = targets->begin();
 508                 MSHR::TargetList::iterator end = targets->end();
 509                 for (; i != end; ++i) {
 510                     Packet * target = *i;
 511                     // If the target contains data, and it overlaps the
 512                     // probed request, need to update data
 513                     if (target->isWrite() && target->intersect(pkt)) {
 514                         uint8_t* pkt_data;
 515                         uint8_t* write_data;
 516                         int data_size;
 517                         if (target->getAddr() < pkt->getAddr()) {
 518                             int offset = pkt->getAddr() - target->getAddr();
 519                             pkt_data = pkt->getPtr<uint8_t>();
 520                             write_data = target->getPtr<uint8_t>() + offset;
 521                             data_size = target->getSize() - offset;
 522                             assert(data_size > 0);
 523                             if (data_size > pkt->getSize())
 524                                 data_size = pkt->getSize();
 525                         } else {
 526                             int offset = target->getAddr() - pkt->getAddr();
 527                             pkt_data = pkt->getPtr<uint8_t>() + offset;
 528                             write_data = target->getPtr<uint8_t>();
 529                             data_size = pkt->getSize() - offset;
 530                             assert(data_size > pkt->getSize());
 531                             if (data_size > target->getSize())
 532                                 data_size = target->getSize();
 533                         }
 534
 535                         if (pkt->isWrite()) {
 536                             memcpy(pkt_data, write_data, data_size);
 537                         } else {
 538                             memcpy(write_data, pkt_data, data_size);
 539                         }
 540                     }
 541                 }
 542             }
 543             for (int i = 0; i < writes.size(); ++i) {
 544                 Packet * write = writes[i]->pkt;
 545                 if (write->intersect(pkt)) {
 546                     warn("Found outstanding write on an non-update probe");
 547                     uint8_t* pkt_data;
 548                     uint8_t* write_data;
 549                     int data_size;
 550                     if (write->getAddr() < pkt->getAddr()) {
 551                         int offset = pkt->getAddr() - write->getAddr();
 552                         pkt_data = pkt->getPtr<uint8_t>();
 553                         write_data = write->getPtr<uint8_t>() + offset;
 554                         data_size = write->getSize() - offset;
 555                         assert(data_size > 0);
 556                         if (data_size > pkt->getSize())
 557                             data_size = pkt->getSize();
 558                     } else {
 559                         int offset = write->getAddr() - pkt->getAddr();
 560                         pkt_data = pkt->getPtr<uint8_t>() + offset;
 561                         write_data = write->getPtr<uint8_t>();
 562                         data_size = pkt->getSize() - offset;
 563                         assert(data_size > pkt->getSize());
 564                         if (data_size > write->getSize())
 565                             data_size = write->getSize();
 566                     }
 567
 568                     if (pkt->isWrite()) {
 569                         memcpy(pkt_data, write_data, data_size);
 570                     } else {
 571                         memcpy(write_data, pkt_data, data_size);
 572                     }
 573
 574                 }
 575             }
 576             return 0;
 577         } else {
 578             // update the cache state and statistics
 579             if (mshr || !writes.empty()){
 580                 // Can't handle it, return pktuest unsatisfied.
 581                 return 0;
 582             }
 583             if (!pkt->req->isUncacheable()) {
 584                 // Fetch the cache block to fill
 585                 BlkType *blk = tags->findBlock(pkt);
 586                 Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
 587                                                    (blk)? blk->status : 0);
 588
 589                 Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
 590
 591                 uint8_t* temp_data = new uint8_t[blkSize];
 592                 busPkt->dataDynamicArray<uint8_t>(temp_data);
 593
 594                 busPkt->time = curTick;
 595
 596                 lat = memSidePort->sendAtomic(busPkt);
 597
 598                 if (!(busPkt->flags & SATISFIED)) {
 599                     // blocked at a higher level, just return
 600                     return 0;
 601                 }
 602
 603                 misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 604
 605                 CacheBlk::State old_state = (blk) ? blk->status : 0;
 606                 tags->handleFill(blk, busPkt,
 607                                  coherence->getNewState(busPkt, old_state),
 608                                  writebacks, pkt);
 609                 // Handle writebacks if needed
 610                 while (!writebacks.empty()){
 611                     memSidePort->sendAtomic(writebacks.front());
 612                     writebacks.pop_front();
 613                 }
 614                 return lat + hitLatency;
 615             } else {
 616                 return memSidePort->sendAtomic(pkt);
 617             }
 618         }
 619     } else {
 620         // There was a cache hit.
 621         // Handle writebacks if needed
 622         while (!writebacks.empty()){
 623             memSidePort->sendAtomic(writebacks.front());
 624             writebacks.pop_front();
 625         }
 626
 627         if (update) {
 628             hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 629         } else if (pkt->isWrite()) {
 630             // Still need to change data in all locations.
 631             return memSidePort->sendAtomic(pkt);
 632         }
 633         return curTick + lat;
 634     }
 635     fatal("Probe not handled.\n");
 636     return 0;
 637 }
 638
 639 template<class TagStore, class Buffering, class Coherence>
 640 Tick
 641 Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt, bool update)
 642 {
 643     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
 644     BlkType *blk = tags->findBlock(pkt);
 645     MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
 646     CacheBlk::State new_state = 0;
 647     bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
 648     if (satisfy) {
 649         tags->handleSnoop(blk, new_state, pkt);
 650         return hitLatency;
 651     }
 652     tags->handleSnoop(blk, new_state);
 653     return 0;
 654 }
 655