2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Erik Hallnor
53 #include "base/fast_alloc.hh"
54 #include "base/misc.hh"
55 #include "base/range.hh"
56 #include "base/types.hh"
57 #include "debug/Cache.hh"
58 #include "debug/CachePort.hh"
59 #include "mem/cache/prefetch/base.hh"
60 #include "mem/cache/blk.hh"
61 #include "mem/cache/cache.hh"
62 #include "mem/cache/mshr.hh"
63 #include "sim/sim_exit.hh"
65 template<class TagStore>
66 Cache<TagStore>::Cache(const Params *p, TagStore *tags, BasePrefetcher *pf)
71 prefetchOnAccess(p->prefetch_on_access)
73 tempBlock = new BlkType();
74 tempBlock->data = new uint8_t[blkSize];
76 cpuSidePort = new CpuSidePort(p->name + "-cpu_side_port", this,
78 memSidePort = new MemSidePort(p->name + "-mem_side_port", this,
80 cpuSidePort->setOtherPort(memSidePort);
81 memSidePort->setOtherPort(cpuSidePort);
85 prefetcher->setCache(this);
88 template<class TagStore>
90 Cache<TagStore>::regStats()
92 BaseCache::regStats();
93 tags->regStats(name());
95 prefetcher->regStats(name());
98 template<class TagStore>
100 Cache<TagStore>::getPort(const std::string &if_name, int idx)
102 if (if_name == "" || if_name == "cpu_side") {
104 } else if (if_name == "mem_side") {
106 } else if (if_name == "functional") {
107 CpuSidePort *funcPort =
108 new CpuSidePort(name() + "-cpu_side_funcport", this,
110 funcPort->setOtherPort(memSidePort);
113 panic("Port name %s unrecognized\n", if_name);
117 template<class TagStore>
119 Cache<TagStore>::deletePortRefs(Port *p)
121 if (cpuSidePort == p || memSidePort == p)
122 panic("Can only delete functional ports\n");
128 template<class TagStore>
130 Cache<TagStore>::cmpAndSwap(BlkType *blk, PacketPtr pkt)
132 uint64_t overwrite_val;
134 uint64_t condition_val64;
135 uint32_t condition_val32;
137 int offset = tags->extractBlkOffset(pkt->getAddr());
138 uint8_t *blk_data = blk->data + offset;
140 assert(sizeof(uint64_t) >= pkt->getSize());
142 overwrite_mem = true;
143 // keep a copy of our possible write value, and copy what is at the
144 // memory address into the packet
145 pkt->writeData((uint8_t *)&overwrite_val);
146 pkt->setData(blk_data);
148 if (pkt->req->isCondSwap()) {
149 if (pkt->getSize() == sizeof(uint64_t)) {
150 condition_val64 = pkt->req->getExtraData();
151 overwrite_mem = !std::memcmp(&condition_val64, blk_data,
153 } else if (pkt->getSize() == sizeof(uint32_t)) {
154 condition_val32 = (uint32_t)pkt->req->getExtraData();
155 overwrite_mem = !std::memcmp(&condition_val32, blk_data,
158 panic("Invalid size for conditional read/write\n");
162 std::memcpy(blk_data, &overwrite_val, pkt->getSize());
163 blk->status |= BlkDirty;
168 template<class TagStore>
170 Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
171 bool deferred_response,
172 bool pending_downgrade)
174 assert(blk && blk->isValid());
175 // Occasionally this is not true... if we are a lower-level cache
176 // satisfying a string of Read and ReadEx requests from
177 // upper-level caches, a Read will mark the block as shared but we
178 // can satisfy a following ReadEx anyway since we can rely on the
179 // Read requester(s) to have buffered the ReadEx snoop and to
180 // invalidate their blocks after receiving them.
181 // assert(!pkt->needsExclusive() || blk->isWritable());
182 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
184 // Check RMW operations first since both isRead() and
185 // isWrite() will be true for them
186 if (pkt->cmd == MemCmd::SwapReq) {
187 cmpAndSwap(blk, pkt);
188 } else if (pkt->isWrite()) {
189 if (blk->checkWrite(pkt)) {
190 pkt->writeDataToBlock(blk->data, blkSize);
191 blk->status |= BlkDirty;
193 } else if (pkt->isRead()) {
195 blk->trackLoadLocked(pkt);
197 pkt->setDataFromBlock(blk->data, blkSize);
198 if (pkt->getSize() == blkSize) {
199 // special handling for coherent block requests from
200 // upper-level caches
201 if (pkt->needsExclusive()) {
202 // if we have a dirty copy, make sure the recipient
203 // keeps it marked dirty
204 if (blk->isDirty()) {
205 pkt->assertMemInhibit();
207 // on ReadExReq we give up our copy unconditionally
208 tags->invalidateBlk(blk);
209 } else if (blk->isWritable() && !pending_downgrade
210 && !pkt->sharedAsserted()) {
211 // we can give the requester an exclusive copy (by not
212 // asserting shared line) on a read request if:
213 // - we have an exclusive copy at this level (& below)
214 // - we don't have a pending snoop from below
215 // signaling another read request
216 // - no other cache above has a copy (otherwise it
217 // would have asseretd shared line on request)
219 if (blk->isDirty()) {
220 // special considerations if we're owner:
221 if (!deferred_response && !isTopLevel) {
222 // if we are responding immediately and can
223 // signal that we're transferring ownership
224 // along with exclusivity, do so
225 pkt->assertMemInhibit();
226 blk->status &= ~BlkDirty;
228 // if we're responding after our own miss,
229 // there's a window where the recipient didn't
230 // know it was getting ownership and may not
231 // have responded to snoops correctly, so we
232 // can't pass off ownership *or* exclusivity
237 // otherwise only respond with a shared copy
242 // Not a read or write... must be an upgrade. it's OK
243 // to just ack those as long as we have an exclusive
244 // copy at this level.
245 assert(pkt->isUpgrade());
246 tags->invalidateBlk(blk);
251 /////////////////////////////////////////////////////
253 // MSHR helper functions
255 /////////////////////////////////////////////////////
258 template<class TagStore>
260 Cache<TagStore>::markInService(MSHR *mshr, PacketPtr pkt)
262 markInServiceInternal(mshr, pkt);
264 if (mshr->originalCmd == MemCmd::HardPFReq) {
265 DPRINTF(HWPrefetch, "%s:Marking a HW_PF in service\n",
267 //Also clear pending if need be
268 if (!prefetcher->havePending())
270 deassertMemSideBusRequest(Request_PF);
277 template<class TagStore>
279 Cache<TagStore>::squash(int threadNum)
281 bool unblock = false;
282 BlockedCause cause = NUM_BLOCKED_CAUSES;
284 if (noTargetMSHR && noTargetMSHR->threadNum == threadNum) {
287 cause = Blocked_NoTargets;
289 if (mshrQueue.isFull()) {
291 cause = Blocked_NoMSHRs;
293 mshrQueue.squash(threadNum);
294 if (unblock && !mshrQueue.isFull()) {
299 /////////////////////////////////////////////////////
301 // Access path: requests coming in from the CPU side
303 /////////////////////////////////////////////////////
305 template<class TagStore>
307 Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
308 int &lat, PacketList &writebacks)
310 if (pkt->req->isUncacheable()) {
311 if (pkt->req->isClearLL()) {
314 blk = tags->findBlock(pkt->getAddr());
316 tags->invalidateBlk(blk);
325 int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
326 blk = tags->accessBlock(pkt->getAddr(), lat, id);
328 DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
329 pkt->req->isInstFetch() ? " (ifetch)" : "",
330 pkt->getAddr(), (blk) ? "hit" : "miss");
334 if (pkt->needsExclusive() ? blk->isWritable() : blk->isReadable()) {
335 // OK to satisfy access
336 incHitCount(pkt, id);
337 satisfyCpuSideRequest(pkt, blk);
342 // Can't satisfy access normally... either no block (blk == NULL)
343 // or have block but need exclusive & only have shared.
345 // Writeback handling is special case. We can write the block
346 // into the cache without having a writeable copy (or any copy at
348 if (pkt->cmd == MemCmd::Writeback) {
349 assert(blkSize == pkt->getSize());
351 // need to do a replacement
352 blk = allocateBlock(pkt->getAddr(), writebacks);
354 // no replaceable block available, give up.
355 // writeback will be forwarded to next level.
356 incMissCount(pkt, id);
359 int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
360 tags->insertBlock(pkt->getAddr(), blk, id);
361 blk->status = BlkValid | BlkReadable;
363 std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
364 blk->status |= BlkDirty;
365 if (pkt->isSupplyExclusive()) {
366 blk->status |= BlkWritable;
368 // nothing else to do; writeback doesn't expect response
369 assert(!pkt->needsResponse());
370 incHitCount(pkt, id);
374 incMissCount(pkt, id);
376 if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) {
377 // complete miss on store conditional... just give up now
378 pkt->req->setExtraData(0);
386 class ForwardResponseRecord : public Packet::SenderState, public FastAlloc
388 Packet::SenderState *prevSenderState;
394 ForwardResponseRecord(Packet *pkt, BaseCache *_cache)
395 : prevSenderState(pkt->senderState), prevSrc(pkt->getSrc())
400 void restore(Packet *pkt, BaseCache *_cache)
402 assert(_cache == cache);
403 pkt->senderState = prevSenderState;
404 pkt->setDest(prevSrc);
409 template<class TagStore>
411 Cache<TagStore>::timingAccess(PacketPtr pkt)
413 //@todo Add back in MemDebug Calls
414 // MemDebug::cacheAccess(pkt);
416 // we charge hitLatency for doing just about anything here
417 Tick time = curTick() + hitLatency;
419 if (pkt->isResponse()) {
420 // must be cache-to-cache response from upper to lower level
421 ForwardResponseRecord *rec =
422 dynamic_cast<ForwardResponseRecord *>(pkt->senderState);
424 rec->restore(pkt, this);
426 memSidePort->respond(pkt, time);
430 assert(pkt->isRequest());
432 if (pkt->memInhibitAsserted()) {
433 DPRINTF(Cache, "mem inhibited on 0x%x: not responding\n",
435 assert(!pkt->req->isUncacheable());
436 // Special tweak for multilevel coherence: snoop downward here
437 // on invalidates since there may be other caches below here
438 // that have shared copies. Not necessary if we know that
439 // supplier had exclusive copy to begin with.
440 if (pkt->needsExclusive() && !pkt->isSupplyExclusive()) {
441 Packet *snoopPkt = new Packet(pkt, true); // clear flags
442 snoopPkt->setExpressSnoop();
443 snoopPkt->assertMemInhibit();
444 memSidePort->sendTiming(snoopPkt);
445 // main memory will delete snoopPkt
447 // since we're the official target but we aren't responding,
448 // delete the packet now.
453 if (pkt->req->isUncacheable()) {
454 if (pkt->req->isClearLL()) {
457 BlkType *blk = tags->findBlock(pkt->getAddr());
459 tags->invalidateBlk(blk);
463 // writes go in write buffer, reads use MSHR
464 if (pkt->isWrite() && !pkt->isRead()) {
465 allocateWriteBuffer(pkt, time, true);
467 allocateUncachedReadBuffer(pkt, time, true);
469 assert(pkt->needsResponse()); // else we should delete it here??
473 int lat = hitLatency;
475 PacketList writebacks;
477 bool satisfied = access(pkt, blk, lat, writebacks);
480 /** @todo make the fast write alloc (wh64) work with coherence. */
482 // If this is a block size write/hint (WH64) allocate the block here
483 // if the coherence protocol allows it.
484 if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
485 (pkt->cmd == MemCmd::WriteReq
486 || pkt->cmd == MemCmd::WriteInvalidateReq) ) {
487 // not outstanding misses, can do this
488 MSHR *outstanding_miss = mshrQueue.findMatch(pkt->getAddr());
489 if (pkt->cmd == MemCmd::WriteInvalidateReq || !outstanding_miss) {
490 if (outstanding_miss) {
491 warn("WriteInv doing a fastallocate"
492 "with an outstanding miss to the same address\n");
494 blk = handleFill(NULL, pkt, BlkValid | BlkWritable,
501 // track time of availability of next prefetch, if any
502 Tick next_pf_time = 0;
504 bool needsResponse = pkt->needsResponse();
508 pkt->makeTimingResponse();
509 cpuSidePort->respond(pkt, curTick()+lat);
514 if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) {
516 blk->status &= ~BlkHWPrefetched;
517 next_pf_time = prefetcher->notify(pkt, time);
522 Addr blk_addr = blockAlign(pkt->getAddr());
523 MSHR *mshr = mshrQueue.findMatch(blk_addr);
527 //@todo remove hw_pf here
528 mshr_hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
529 if (mshr->threadNum != 0/*pkt->req->threadId()*/) {
530 mshr->threadNum = -1;
532 mshr->allocateTarget(pkt, time, order++);
533 if (mshr->getNumTargets() == numTarget) {
535 setBlocked(Blocked_NoTargets);
536 // need to be careful with this... if this mshr isn't
537 // ready yet (i.e. time > curTick()_, we don't want to
538 // move it ahead of mshrs that are ready
539 // mshrQueue.moveToFront(mshr);
543 mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
544 // always mark as cache fill for now... if we implement
545 // no-write-allocate or bypass accesses this will have to
547 if (pkt->cmd == MemCmd::Writeback) {
548 allocateWriteBuffer(pkt, time, true);
550 if (blk && blk->isValid()) {
551 // If we have a write miss to a valid block, we
552 // need to mark the block non-readable. Otherwise
553 // if we allow reads while there's an outstanding
554 // write miss, the read could return stale data
555 // out of the cache block... a more aggressive
556 // system could detect the overlap (if any) and
557 // forward data out of the MSHRs, but we don't do
558 // that yet. Note that we do need to leave the
559 // block valid so that it stays in the cache, in
560 // case we get an upgrade response (and hence no
561 // new data) when the write miss completes.
562 // As long as CPUs do proper store/load forwarding
563 // internally, and have a sufficiently weak memory
564 // model, this is probably unnecessary, but at some
565 // point it must have seemed like we needed it...
566 assert(pkt->needsExclusive() && !blk->isWritable());
567 blk->status &= ~BlkReadable;
570 allocateMissBuffer(pkt, time, true);
574 next_pf_time = prefetcher->notify(pkt, time);
579 if (next_pf_time != 0)
580 requestMemSideBus(Request_PF, std::max(time, next_pf_time));
582 // copy writebacks to write buffer
583 while (!writebacks.empty()) {
584 PacketPtr wbPkt = writebacks.front();
585 allocateWriteBuffer(wbPkt, time, true);
586 writebacks.pop_front();
593 // See comment in cache.hh.
594 template<class TagStore>
596 Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
599 bool blkValid = blk && blk->isValid();
601 if (cpu_pkt->req->isUncacheable()) {
602 //assert(blk == NULL);
607 (cpu_pkt->cmd == MemCmd::Writeback || cpu_pkt->isUpgrade())) {
608 // Writebacks that weren't allocated in access() and upgrades
609 // from upper-level caches that missed completely just go
614 assert(cpu_pkt->needsResponse());
617 // @TODO make useUpgrades a parameter.
618 // Note that ownership protocols require upgrade, otherwise a
619 // write miss on a shared owned block will generate a ReadExcl,
620 // which will clobber the owned copy.
621 const bool useUpgrades = true;
622 if (blkValid && useUpgrades) {
623 // only reason to be here is that blk is shared
624 // (read-only) and we need exclusive
625 assert(needsExclusive && !blk->isWritable());
626 cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
629 cmd = needsExclusive ? MemCmd::ReadExReq : MemCmd::ReadReq;
631 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, Packet::Broadcast, blkSize);
638 template<class TagStore>
640 Cache<TagStore>::atomicAccess(PacketPtr pkt)
642 int lat = hitLatency;
644 // @TODO: make this a parameter
645 bool last_level_cache = false;
647 if (pkt->memInhibitAsserted()) {
648 assert(!pkt->req->isUncacheable());
649 // have to invalidate ourselves and any lower caches even if
650 // upper cache will be responding
651 if (pkt->isInvalidate()) {
652 BlkType *blk = tags->findBlock(pkt->getAddr());
653 if (blk && blk->isValid()) {
654 tags->invalidateBlk(blk);
655 DPRINTF(Cache, "rcvd mem-inhibited %s on 0x%x: invalidating\n",
656 pkt->cmdString(), pkt->getAddr());
658 if (!last_level_cache) {
659 DPRINTF(Cache, "forwarding mem-inhibited %s on 0x%x\n",
660 pkt->cmdString(), pkt->getAddr());
661 lat += memSidePort->sendAtomic(pkt);
664 DPRINTF(Cache, "rcvd mem-inhibited %s on 0x%x: not responding\n",
665 pkt->cmdString(), pkt->getAddr());
671 // should assert here that there are no outstanding MSHRs or
672 // writebacks... that would mean that someone used an atomic
673 // access in timing mode
676 PacketList writebacks;
678 if (!access(pkt, blk, lat, writebacks)) {
680 PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsExclusive());
682 bool is_forward = (bus_pkt == NULL);
685 // just forwarding the same request to the next level
686 // no local cache operation involved
690 DPRINTF(Cache, "Sending an atomic %s for %x\n",
691 bus_pkt->cmdString(), bus_pkt->getAddr());
694 CacheBlk::State old_state = blk ? blk->status : 0;
697 lat += memSidePort->sendAtomic(bus_pkt);
699 DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
700 bus_pkt->cmdString(), bus_pkt->getAddr(), old_state);
702 assert(!bus_pkt->wasNacked());
704 // If packet was a forward, the response (if any) is already
705 // in place in the bus_pkt == pkt structure, so we don't need
706 // to do anything. Otherwise, use the separate bus_pkt to
707 // generate response to pkt and then delete it.
709 if (pkt->needsResponse()) {
710 assert(bus_pkt->isResponse());
711 if (bus_pkt->isError()) {
712 pkt->makeAtomicResponse();
713 pkt->copyError(bus_pkt);
714 } else if (bus_pkt->isRead() ||
715 bus_pkt->cmd == MemCmd::UpgradeResp) {
716 // we're updating cache state to allow us to
717 // satisfy the upstream request from the cache
718 blk = handleFill(bus_pkt, blk, writebacks);
719 satisfyCpuSideRequest(pkt, blk);
721 // we're satisfying the upstream request without
722 // modifying cache state, e.g., a write-through
723 pkt->makeAtomicResponse();
730 // Note that we don't invoke the prefetcher at all in atomic mode.
731 // It's not clear how to do it properly, particularly for
732 // prefetchers that aggressively generate prefetch candidates and
733 // rely on bandwidth contention to throttle them; these will tend
734 // to pollute the cache in atomic mode since there is no bandwidth
735 // contention. If we ever do want to enable prefetching in atomic
736 // mode, though, this is the place to do it... see timingAccess()
737 // for an example (though we'd want to issue the prefetch(es)
738 // immediately rather than calling requestMemSideBus() as we do
741 // Handle writebacks if needed
742 while (!writebacks.empty()){
743 PacketPtr wbPkt = writebacks.front();
744 memSidePort->sendAtomic(wbPkt);
745 writebacks.pop_front();
749 // We now have the block one way or another (hit or completed miss)
751 if (pkt->needsResponse()) {
752 pkt->makeAtomicResponse();
759 template<class TagStore>
761 Cache<TagStore>::functionalAccess(PacketPtr pkt,
762 CachePort *incomingPort,
763 CachePort *otherSidePort)
765 Addr blk_addr = blockAlign(pkt->getAddr());
766 BlkType *blk = tags->findBlock(pkt->getAddr());
767 MSHR *mshr = mshrQueue.findMatch(blk_addr);
769 pkt->pushLabel(name());
771 CacheBlkPrintWrapper cbpw(blk);
773 // Note that just because an L2/L3 has valid data doesn't mean an
774 // L1 doesn't have a more up-to-date modified copy that still
775 // needs to be found. As a result we always update the request if
776 // we have it, but only declare it satisfied if we are the owner.
778 // see if we have data at all (owned or otherwise)
779 bool have_data = blk && blk->isValid()
780 && pkt->checkFunctional(&cbpw, blk_addr, blkSize, blk->data);
782 // data we have is dirty if marked as such or if valid & ownership
783 // pending due to outstanding UpgradeReq
785 have_data && (blk->isDirty() ||
786 (mshr && mshr->inService && mshr->isPendingDirty()));
788 bool done = have_dirty
789 || incomingPort->checkFunctional(pkt)
790 || mshrQueue.checkFunctional(pkt, blk_addr)
791 || writeBuffer.checkFunctional(pkt, blk_addr)
792 || otherSidePort->checkFunctional(pkt);
794 DPRINTF(Cache, "functional %s %x %s%s%s\n",
795 pkt->cmdString(), pkt->getAddr(),
796 (blk && blk->isValid()) ? "valid " : "",
797 have_data ? "data " : "", done ? "done " : "");
799 // We're leaving the cache, so pop cache->name() label
805 otherSidePort->sendFunctional(pkt);
810 /////////////////////////////////////////////////////
812 // Response handling: responses from the memory side
814 /////////////////////////////////////////////////////
817 template<class TagStore>
819 Cache<TagStore>::handleResponse(PacketPtr pkt)
821 Tick time = curTick() + hitLatency;
822 MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
823 bool is_error = pkt->isError();
827 if (pkt->wasNacked()) {
828 //pkt->reinitFromRequest();
829 warn("NACKs from devices not connected to the same bus "
830 "not implemented\n");
834 DPRINTF(Cache, "Cache received packet with error for address %x, "
835 "cmd: %s\n", pkt->getAddr(), pkt->cmdString());
838 DPRINTF(Cache, "Handling response to %x\n", pkt->getAddr());
840 MSHRQueue *mq = mshr->queue;
841 bool wasFull = mq->isFull();
843 if (mshr == noTargetMSHR) {
844 // we always clear at least one target
845 clearBlocked(Blocked_NoTargets);
849 // Initial target is used just for stats
850 MSHR::Target *initial_tgt = mshr->getTarget();
851 BlkType *blk = tags->findBlock(pkt->getAddr());
852 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
853 Tick miss_latency = curTick() - initial_tgt->recvTime;
854 PacketList writebacks;
856 if (pkt->req->isUncacheable()) {
857 mshr_uncacheable_lat[stats_cmd_idx][0/*pkt->req->threadId()*/] +=
860 mshr_miss_latency[stats_cmd_idx][0/*pkt->req->threadId()*/] +=
864 bool is_fill = !mshr->isForward &&
865 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
867 if (is_fill && !is_error) {
868 DPRINTF(Cache, "Block for addr %x being updated in Cache\n",
871 // give mshr a chance to do some dirty work
872 mshr->handleFill(pkt, blk);
874 blk = handleFill(pkt, blk, writebacks);
878 // First offset for critical word first calculations
879 int initial_offset = 0;
881 if (mshr->hasTargets()) {
882 initial_offset = mshr->getTarget()->pkt->getOffset(blkSize);
885 while (mshr->hasTargets()) {
886 MSHR::Target *target = mshr->getTarget();
888 switch (target->source) {
889 case MSHR::Target::FromCPU:
890 Tick completion_time;
892 satisfyCpuSideRequest(target->pkt, blk,
893 true, mshr->hasPostDowngrade());
894 // How many bytes past the first request is this one
895 int transfer_offset =
896 target->pkt->getOffset(blkSize) - initial_offset;
897 if (transfer_offset < 0) {
898 transfer_offset += blkSize;
901 // If critical word (no offset) return first word time
902 completion_time = tags->getHitLatency() +
903 (transfer_offset ? pkt->finishTime : pkt->firstWordTime);
905 assert(!target->pkt->req->isUncacheable());
906 missLatency[target->pkt->cmdToIndex()][0/*pkt->req->threadId()*/] +=
907 completion_time - target->recvTime;
908 } else if (pkt->cmd == MemCmd::UpgradeFailResp) {
909 // failed StoreCond upgrade
910 assert(target->pkt->cmd == MemCmd::StoreCondReq ||
911 target->pkt->cmd == MemCmd::StoreCondFailReq ||
912 target->pkt->cmd == MemCmd::SCUpgradeFailReq);
913 completion_time = tags->getHitLatency() + pkt->finishTime;
914 target->pkt->req->setExtraData(0);
916 // not a cache fill, just forwarding response
917 completion_time = tags->getHitLatency() + pkt->finishTime;
918 if (pkt->isRead() && !is_error) {
919 target->pkt->setData(pkt->getPtr<uint8_t>());
922 target->pkt->makeTimingResponse();
923 // if this packet is an error copy that to the new packet
925 target->pkt->copyError(pkt);
926 if (target->pkt->cmd == MemCmd::ReadResp &&
927 (pkt->isInvalidate() || mshr->hasPostInvalidate())) {
928 // If intermediate cache got ReadRespWithInvalidate,
929 // propagate that. Response should not have
930 // isInvalidate() set otherwise.
931 target->pkt->cmd = MemCmd::ReadRespWithInvalidate;
933 cpuSidePort->respond(target->pkt, completion_time);
936 case MSHR::Target::FromPrefetcher:
937 assert(target->pkt->cmd == MemCmd::HardPFReq);
939 blk->status |= BlkHWPrefetched;
940 delete target->pkt->req;
944 case MSHR::Target::FromSnoop:
945 // I don't believe that a snoop can be in an error state
947 // response to snoop request
948 DPRINTF(Cache, "processing deferred snoop...\n");
949 assert(!(pkt->isInvalidate() && !mshr->hasPostInvalidate()));
950 handleSnoop(target->pkt, blk, true, true,
951 mshr->hasPostInvalidate());
955 panic("Illegal target->source enum %d\n", target->source);
962 if (pkt->isInvalidate() || mshr->hasPostInvalidate()) {
963 tags->invalidateBlk(blk);
964 } else if (mshr->hasPostDowngrade()) {
965 blk->status &= ~BlkWritable;
969 if (mshr->promoteDeferredTargets()) {
970 // avoid later read getting stale data while write miss is
971 // outstanding.. see comment in timingAccess()
973 blk->status &= ~BlkReadable;
975 MSHRQueue *mq = mshr->queue;
976 mq->markPending(mshr);
977 requestMemSideBus((RequestCause)mq->index, pkt->finishTime);
979 mq->deallocate(mshr);
980 if (wasFull && !mq->isFull()) {
981 clearBlocked((BlockedCause)mq->index);
985 // copy writebacks to write buffer
986 while (!writebacks.empty()) {
987 PacketPtr wbPkt = writebacks.front();
988 allocateWriteBuffer(wbPkt, time, true);
989 writebacks.pop_front();
991 // if we used temp block, clear it out
992 if (blk == tempBlock) {
993 if (blk->isDirty()) {
994 allocateWriteBuffer(writebackBlk(blk), time, true);
996 tags->invalidateBlk(blk);
1005 template<class TagStore>
1007 Cache<TagStore>::writebackBlk(BlkType *blk)
1009 assert(blk && blk->isValid() && blk->isDirty());
1011 writebacks[0/*pkt->req->threadId()*/]++;
1013 Request *writebackReq =
1014 new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0);
1015 PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1);
1016 if (blk->isWritable()) {
1017 writeback->setSupplyExclusive();
1019 writeback->allocate();
1020 std::memcpy(writeback->getPtr<uint8_t>(), blk->data, blkSize);
1022 blk->status &= ~BlkDirty;
1027 template<class TagStore>
1028 typename Cache<TagStore>::BlkType*
1029 Cache<TagStore>::allocateBlock(Addr addr, PacketList &writebacks)
1031 BlkType *blk = tags->findVictim(addr, writebacks);
1033 if (blk->isValid()) {
1034 Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set);
1035 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr);
1037 // must be an outstanding upgrade request on block
1038 // we're about to replace...
1039 assert(!blk->isWritable());
1040 assert(repl_mshr->needsExclusive());
1041 // too hard to replace block with transient state
1042 // allocation failed, block not inserted
1045 DPRINTF(Cache, "replacement: replacing %x with %x: %s\n",
1047 blk->isDirty() ? "writeback" : "clean");
1049 if (blk->isDirty()) {
1050 // Save writeback packet for handling by caller
1051 writebacks.push_back(writebackBlk(blk));
1060 // Note that the reason we return a list of writebacks rather than
1061 // inserting them directly in the write buffer is that this function
1062 // is called by both atomic and timing-mode accesses, and in atomic
1063 // mode we don't mess with the write buffer (we just perform the
1064 // writebacks atomically once the original request is complete).
1065 template<class TagStore>
1066 typename Cache<TagStore>::BlkType*
1067 Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
1068 PacketList &writebacks)
1070 Addr addr = pkt->getAddr();
1072 CacheBlk::State old_state = blk ? blk->status : 0;
1076 // better have read new data...
1077 assert(pkt->hasData());
1078 // need to do a replacement
1079 blk = allocateBlock(addr, writebacks);
1081 // No replaceable block... just use temporary storage to
1082 // complete the current request and then get rid of it
1083 assert(!tempBlock->isValid());
1085 tempBlock->set = tags->extractSet(addr);
1086 tempBlock->tag = tags->extractTag(addr);
1087 DPRINTF(Cache, "using temp block for %x\n", addr);
1089 int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
1090 tags->insertBlock(pkt->getAddr(), blk, id);
1093 // starting from scratch with a new block
1096 // existing block... probably an upgrade
1097 assert(blk->tag == tags->extractTag(addr));
1098 // either we're getting new data or the block should already be valid
1099 assert(pkt->hasData() || blk->isValid());
1100 // don't clear block status... if block is already dirty we
1101 // don't want to lose that
1104 blk->status |= BlkValid | BlkReadable;
1106 if (!pkt->sharedAsserted()) {
1107 blk->status |= BlkWritable;
1108 // If we got this via cache-to-cache transfer (i.e., from a
1109 // cache that was an owner) and took away that owner's copy,
1110 // then we need to write it back. Normally this happens
1111 // anyway as a side effect of getting a copy to write it, but
1112 // there are cases (such as failed store conditionals or
1113 // compare-and-swaps) where we'll demand an exclusive copy but
1114 // end up not writing it.
1115 if (pkt->memInhibitAsserted())
1116 blk->status |= BlkDirty;
1119 DPRINTF(Cache, "Block addr %x moving from state %i to %i\n",
1120 addr, old_state, blk->status);
1122 // if we got new data, copy it in
1123 if (pkt->isRead()) {
1124 std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
1127 blk->whenReady = pkt->finishTime;
1133 /////////////////////////////////////////////////////
1135 // Snoop path: requests coming in from the memory side
1137 /////////////////////////////////////////////////////
1139 template<class TagStore>
1142 doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
1143 bool already_copied, bool pending_inval)
1145 // timing-mode snoop responses require a new packet, unless we
1146 // already made a copy...
1147 PacketPtr pkt = already_copied ? req_pkt : new Packet(req_pkt);
1148 assert(req_pkt->isInvalidate() || pkt->sharedAsserted());
1150 pkt->makeTimingResponse();
1151 if (pkt->isRead()) {
1152 pkt->setDataFromBlock(blk_data, blkSize);
1154 if (pkt->cmd == MemCmd::ReadResp && pending_inval) {
1155 // Assume we defer a response to a read from a far-away cache
1156 // A, then later defer a ReadExcl from a cache B on the same
1157 // bus as us. We'll assert MemInhibit in both cases, but in
1158 // the latter case MemInhibit will keep the invalidation from
1159 // reaching cache A. This special response tells cache A that
1160 // it gets the block to satisfy its read, but must immediately
1162 pkt->cmd = MemCmd::ReadRespWithInvalidate;
1164 memSidePort->respond(pkt, curTick() + hitLatency);
1167 template<class TagStore>
1169 Cache<TagStore>::handleSnoop(PacketPtr pkt, BlkType *blk,
1170 bool is_timing, bool is_deferred,
1173 // deferred snoops can only happen in timing mode
1174 assert(!(is_deferred && !is_timing));
1175 // pending_inval only makes sense on deferred snoops
1176 assert(!(pending_inval && !is_deferred));
1177 assert(pkt->isRequest());
1179 // the packet may get modified if we or a forwarded snooper
1180 // responds in atomic mode, so remember a few things about the
1181 // original packet up front
1182 bool invalidate = pkt->isInvalidate();
1183 bool M5_VAR_USED needs_exclusive = pkt->needsExclusive();
1185 if (forwardSnoops) {
1186 // first propagate snoop upward to see if anyone above us wants to
1187 // handle it. save & restore packet src since it will get
1188 // rewritten to be relative to cpu-side bus (if any)
1189 bool alreadyResponded = pkt->memInhibitAsserted();
1191 Packet *snoopPkt = new Packet(pkt, true); // clear flags
1192 snoopPkt->setExpressSnoop();
1193 snoopPkt->senderState = new ForwardResponseRecord(pkt, this);
1194 cpuSidePort->sendTiming(snoopPkt);
1195 if (snoopPkt->memInhibitAsserted()) {
1196 // cache-to-cache response from some upper cache
1197 assert(!alreadyResponded);
1198 pkt->assertMemInhibit();
1200 delete snoopPkt->senderState;
1202 if (snoopPkt->sharedAsserted()) {
1203 pkt->assertShared();
1207 int origSrc = pkt->getSrc();
1208 cpuSidePort->sendAtomic(pkt);
1209 if (!alreadyResponded && pkt->memInhibitAsserted()) {
1210 // cache-to-cache response from some upper cache:
1211 // forward response to original requester
1212 assert(pkt->isResponse());
1214 pkt->setSrc(origSrc);
1218 if (!blk || !blk->isValid()) {
1222 // we may end up modifying both the block state and the packet (if
1223 // we respond in atomic mode), so just figure out what to do now
1224 // and then do it later
1225 bool respond = blk->isDirty() && pkt->needsResponse();
1226 bool have_exclusive = blk->isWritable();
1228 if (pkt->isRead() && !invalidate) {
1229 assert(!needs_exclusive);
1230 pkt->assertShared();
1231 int bits_to_clear = BlkWritable;
1232 const bool haveOwnershipState = true; // for now
1233 if (!haveOwnershipState) {
1234 // if we don't support pure ownership (dirty && !writable),
1235 // have to clear dirty bit here, assume memory snarfs data
1236 // on cache-to-cache xfer
1237 bits_to_clear |= BlkDirty;
1239 blk->status &= ~bits_to_clear;
1242 DPRINTF(Cache, "snooped a %s request for addr %x, %snew state is %i\n",
1243 pkt->cmdString(), blockAlign(pkt->getAddr()),
1244 respond ? "responding, " : "", invalidate ? 0 : blk->status);
1247 assert(!pkt->memInhibitAsserted());
1248 pkt->assertMemInhibit();
1249 if (have_exclusive) {
1250 pkt->setSupplyExclusive();
1253 doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval);
1255 pkt->makeAtomicResponse();
1256 pkt->setDataFromBlock(blk->data, blkSize);
1258 } else if (is_timing && is_deferred) {
1259 // if it's a deferred timing snoop then we've made a copy of
1260 // the packet, and so if we're not using that copy to respond
1261 // then we need to delete it here.
1265 // Do this last in case it deallocates block data or something
1268 tags->invalidateBlk(blk);
1273 template<class TagStore>
1275 Cache<TagStore>::snoopTiming(PacketPtr pkt)
1277 // Note that some deferred snoops don't have requests, since the
1278 // original access may have already completed
1279 if ((pkt->req && pkt->req->isUncacheable()) ||
1280 pkt->cmd == MemCmd::Writeback) {
1281 //Can't get a hit on an uncacheable address
1282 //Revisit this for multi level coherence
1286 BlkType *blk = tags->findBlock(pkt->getAddr());
1288 Addr blk_addr = blockAlign(pkt->getAddr());
1289 MSHR *mshr = mshrQueue.findMatch(blk_addr);
1291 // Let the MSHR itself track the snoop and decide whether we want
1292 // to go ahead and do the regular cache snoop
1293 if (mshr && mshr->handleSnoop(pkt, order++)) {
1294 DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %x\n",
1296 if (mshr->getNumTargets() > numTarget)
1297 warn("allocating bonus target for snoop"); //handle later
1301 //We also need to check the writeback buffers and handle those
1302 std::vector<MSHR *> writebacks;
1303 if (writeBuffer.findMatches(blk_addr, writebacks)) {
1304 DPRINTF(Cache, "Snoop hit in writeback to addr: %x\n",
1307 //Look through writebacks for any non-uncachable writes, use that
1308 for (int i = 0; i < writebacks.size(); i++) {
1309 mshr = writebacks[i];
1310 assert(!mshr->isUncacheable());
1311 assert(mshr->getNumTargets() == 1);
1312 PacketPtr wb_pkt = mshr->getTarget()->pkt;
1313 assert(wb_pkt->cmd == MemCmd::Writeback);
1315 assert(!pkt->memInhibitAsserted());
1316 pkt->assertMemInhibit();
1317 if (!pkt->needsExclusive()) {
1318 pkt->assertShared();
1319 // the writeback is no longer the exclusive copy in the system
1320 wb_pkt->clearSupplyExclusive();
1322 // if we're not asserting the shared line, we need to
1323 // invalidate our copy. we'll do that below as long as
1324 // the packet's invalidate flag is set...
1325 assert(pkt->isInvalidate());
1327 doTimingSupplyResponse(pkt, wb_pkt->getPtr<uint8_t>(),
1330 if (pkt->isInvalidate()) {
1331 // Invalidation trumps our writeback... discard here
1332 markInService(mshr);
1336 // If this was a shared writeback, there may still be
1337 // other shared copies above that require invalidation.
1338 // We could be more selective and return here if the
1339 // request is non-exclusive or if the writeback is
1345 handleSnoop(pkt, blk, true, false, false);
1349 template<class TagStore>
1351 Cache<TagStore>::snoopAtomic(PacketPtr pkt)
1353 if (pkt->req->isUncacheable() || pkt->cmd == MemCmd::Writeback) {
1354 // Can't get a hit on an uncacheable address
1355 // Revisit this for multi level coherence
1359 BlkType *blk = tags->findBlock(pkt->getAddr());
1360 handleSnoop(pkt, blk, false, false, false);
1365 template<class TagStore>
1367 Cache<TagStore>::getNextMSHR()
1369 // Check both MSHR queue and write buffer for potential requests
1370 MSHR *miss_mshr = mshrQueue.getNextMSHR();
1371 MSHR *write_mshr = writeBuffer.getNextMSHR();
1373 // Now figure out which one to send... some cases are easy
1374 if (miss_mshr && !write_mshr) {
1377 if (write_mshr && !miss_mshr) {
1381 if (miss_mshr && write_mshr) {
1382 // We have one of each... normally we favor the miss request
1383 // unless the write buffer is full
1384 if (writeBuffer.isFull() && writeBuffer.inServiceEntries == 0) {
1385 // Write buffer is full, so we'd like to issue a write;
1386 // need to search MSHR queue for conflicting earlier miss.
1387 MSHR *conflict_mshr =
1388 mshrQueue.findPending(write_mshr->addr, write_mshr->size);
1390 if (conflict_mshr && conflict_mshr->order < write_mshr->order) {
1391 // Service misses in order until conflict is cleared.
1392 return conflict_mshr;
1395 // No conflicts; issue write
1399 // Write buffer isn't full, but need to check it for
1400 // conflicting earlier writeback
1401 MSHR *conflict_mshr =
1402 writeBuffer.findPending(miss_mshr->addr, miss_mshr->size);
1403 if (conflict_mshr) {
1404 // not sure why we don't check order here... it was in the
1405 // original code but commented out.
1407 // The only way this happens is if we are
1408 // doing a write and we didn't have permissions
1409 // then subsequently saw a writeback (owned got evicted)
1410 // We need to make sure to perform the writeback first
1411 // To preserve the dirty data, then we can issue the write
1413 // should we return write_mshr here instead? I.e. do we
1414 // have to flush writes in order? I don't think so... not
1415 // for Alpha anyway. Maybe for x86?
1416 return conflict_mshr;
1419 // No conflicts; issue read
1423 // fall through... no pending requests. Try a prefetch.
1424 assert(!miss_mshr && !write_mshr);
1425 if (prefetcher && !mshrQueue.isFull()) {
1426 // If we have a miss queue slot, we can try a prefetch
1427 PacketPtr pkt = prefetcher->getPacket();
1429 Addr pf_addr = blockAlign(pkt->getAddr());
1430 if (!tags->findBlock(pf_addr) && !mshrQueue.findMatch(pf_addr)) {
1431 // Update statistic on number of prefetches issued
1432 // (hwpf_mshr_misses)
1433 mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
1434 // Don't request bus, since we already have it
1435 return allocateMissBuffer(pkt, curTick(), false);
1444 template<class TagStore>
1446 Cache<TagStore>::getTimingPacket()
1448 MSHR *mshr = getNextMSHR();
1454 // use request from 1st target
1455 PacketPtr tgt_pkt = mshr->getTarget()->pkt;
1456 PacketPtr pkt = NULL;
1458 if (tgt_pkt->cmd == MemCmd::SCUpgradeFailReq ||
1459 tgt_pkt->cmd == MemCmd::StoreCondFailReq) {
1460 // SCUpgradeReq or StoreCondReq saw invalidation while queued
1461 // in MSHR, so now that we are getting around to processing
1462 // it, just treat it as if we got a failure response
1463 pkt = new Packet(tgt_pkt);
1464 pkt->cmd = MemCmd::UpgradeFailResp;
1465 pkt->senderState = mshr;
1466 pkt->firstWordTime = pkt->finishTime = curTick();
1467 handleResponse(pkt);
1469 } else if (mshr->isForwardNoResponse()) {
1470 // no response expected, just forward packet as it is
1471 assert(tags->findBlock(mshr->addr) == NULL);
1474 BlkType *blk = tags->findBlock(mshr->addr);
1475 pkt = getBusPacket(tgt_pkt, blk, mshr->needsExclusive());
1477 mshr->isForward = (pkt == NULL);
1479 if (mshr->isForward) {
1480 // not a cache block request, but a response is expected
1481 // make copy of current packet to forward, keep current
1482 // copy for response handling
1483 pkt = new Packet(tgt_pkt);
1485 if (pkt->isWrite()) {
1486 pkt->setData(tgt_pkt->getPtr<uint8_t>());
1491 assert(pkt != NULL);
1492 pkt->senderState = mshr;
1497 template<class TagStore>
1499 Cache<TagStore>::nextMSHRReadyTime()
1501 Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(),
1502 writeBuffer.nextMSHRReadyTime());
1505 nextReady = std::min(nextReady,
1506 prefetcher->nextPrefetchReadyTime());
1519 template<class TagStore>
1521 Cache<TagStore>::CpuSidePort::
1522 getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
1524 // CPU side port doesn't snoop; it's a target only. It can
1525 // potentially respond to any address.
1527 resp.push_back(myCache()->getAddrRange());
1531 template<class TagStore>
1533 Cache<TagStore>::CpuSidePort::recvTiming(PacketPtr pkt)
1535 // illegal to block responses... can lead to deadlock
1536 if (pkt->isRequest() && !pkt->memInhibitAsserted() && blocked) {
1537 DPRINTF(Cache,"Scheduling a retry while blocked\n");
1538 mustSendRetry = true;
1542 myCache()->timingAccess(pkt);
1547 template<class TagStore>
1549 Cache<TagStore>::CpuSidePort::recvAtomic(PacketPtr pkt)
1551 return myCache()->atomicAccess(pkt);
1555 template<class TagStore>
1557 Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt)
1559 myCache()->functionalAccess(pkt, this, otherPort);
1563 template<class TagStore>
1565 CpuSidePort::CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
1566 const std::string &_label)
1567 : BaseCache::CachePort(_name, _cache, _label)
1577 template<class TagStore>
1579 Cache<TagStore>::MemSidePort::
1580 getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
1582 // Memory-side port always snoops, but never passes requests
1583 // through to targets on the cpu side (so we don't add anything to
1584 // the address range list).
1589 template<class TagStore>
1591 Cache<TagStore>::MemSidePort::recvTiming(PacketPtr pkt)
1593 // this needs to be fixed so that the cache updates the mshr and sends the
1594 // packet back out on the link, but it probably won't happen so until this
1595 // gets fixed, just panic when it does
1596 if (pkt->wasNacked())
1597 panic("Need to implement cache resending nacked packets!\n");
1599 if (pkt->isRequest() && blocked) {
1600 DPRINTF(Cache,"Scheduling a retry while blocked\n");
1601 mustSendRetry = true;
1605 if (pkt->isResponse()) {
1606 myCache()->handleResponse(pkt);
1608 myCache()->snoopTiming(pkt);
1614 template<class TagStore>
1616 Cache<TagStore>::MemSidePort::recvAtomic(PacketPtr pkt)
1618 // in atomic mode, responses go back to the sender via the
1619 // function return from sendAtomic(), not via a separate
1620 // sendAtomic() from the responder. Thus we should never see a
1621 // response packet in recvAtomic() (anywhere, not just here).
1622 assert(!pkt->isResponse());
1623 return myCache()->snoopAtomic(pkt);
1627 template<class TagStore>
1629 Cache<TagStore>::MemSidePort::recvFunctional(PacketPtr pkt)
1631 myCache()->functionalAccess(pkt, this, otherPort);
1636 template<class TagStore>
1638 Cache<TagStore>::MemSidePort::sendPacket()
1640 // if we have responses that are ready, they take precedence
1641 if (deferredPacketReady()) {
1642 bool success = sendTiming(transmitList.front().pkt);
1645 //send successful, remove packet
1646 transmitList.pop_front();
1649 waitingOnRetry = !success;
1651 // check for non-response packets (requests & writebacks)
1652 PacketPtr pkt = myCache()->getTimingPacket();
1654 // can happen if e.g. we attempt a writeback and fail, but
1655 // before the retry, the writeback is eliminated because
1656 // we snoop another cache's ReadEx.
1657 waitingOnRetry = false;
1659 MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
1661 bool success = sendTiming(pkt);
1663 waitingOnRetry = !success;
1664 if (waitingOnRetry) {
1665 DPRINTF(CachePort, "now waiting on a retry\n");
1666 if (!mshr->isForwardNoResponse()) {
1670 myCache()->markInService(mshr, pkt);
1676 // tried to send packet... if it was successful (no retry), see if
1677 // we need to rerequest bus or not
1678 if (!waitingOnRetry) {
1679 Tick nextReady = std::min(deferredPacketReadyTime(),
1680 myCache()->nextMSHRReadyTime());
1681 // @TODO: need to facotr in prefetch requests here somehow
1682 if (nextReady != MaxTick) {
1683 DPRINTF(CachePort, "more packets to send @ %d\n", nextReady);
1684 schedule(sendEvent, std::max(nextReady, curTick() + 1));
1686 // no more to send right now: if we're draining, we may be done
1687 if (drainEvent && !sendEvent->scheduled()) {
1688 drainEvent->process();
1695 template<class TagStore>
1697 Cache<TagStore>::MemSidePort::recvRetry()
1699 assert(waitingOnRetry);
1704 template<class TagStore>
1706 Cache<TagStore>::MemSidePort::processSendEvent()
1708 assert(!waitingOnRetry);
1713 template<class TagStore>
1715 MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
1716 const std::string &_label)
1717 : BaseCache::CachePort(_name, _cache, _label)
1719 // override default send event from SimpleTimingPort
1721 sendEvent = new SendEvent(this);