src/mem/cache/coherence/simple_coherence.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  *          Ron Dreslinski
  30  */
  31
  32 /**
  33  * @file
  34  * Declaration of a simple coherence policy.
  35  */
  36
  37 #ifndef __SIMPLE_COHERENCE_HH__
  38 #define __SIMPLE_COHERENCE_HH__
  39
  40 #include <string>
  41
  42 #include "mem/packet.hh"
  43 #include "mem/cache/cache_blk.hh"
  44 #include "mem/cache/miss/mshr_queue.hh"
  45 #include "mem/cache/coherence/coherence_protocol.hh"
  46
  47 class BaseCache;
  48
  49 /**
  50  * A simple MP coherence policy. This policy assumes an atomic bus and only one
  51  * level of cache.
  52  */
  53 class SimpleCoherence
  54 {
  55   protected:
  56     /** Pointer to the parent cache. */
  57     BaseCache *cache;
  58     /** Pointer to the coherence protocol. */
  59     CoherenceProtocol *protocol;
  60
  61   public:
  62     /**
  63      * Construct and initialize this coherence policy.
  64      * @param _protocol The coherence protocol to use.
  65      */
  66     SimpleCoherence(CoherenceProtocol *_protocol)
  67         : protocol(_protocol)
  68     {
  69     }
  70
  71     /**
  72      * Set the pointer to the parent cache.
  73      * @param _cache The parent cache.
  74      */
  75     void setCache(BaseCache *_cache)
  76     {
  77         cache = _cache;
  78     }
  79
  80     /**
  81      * Register statistics.
  82      * @param name The name to prepend to stat descriptions.
  83      */
  84     void regStats(const std::string &name)
  85     {
  86     }
  87
  88     /**
  89      * This policy does not forward invalidates, return NULL.
  90      * @return NULL.
  91      */
  92     PacketPtr getPacket()
  93     {
  94         return NULL;
  95     }
  96
  97     /**
  98      * Was the CSHR request was sent successfully?
  99      * @param pkt The request.
 100      * @param success True if the request was sent successfully.
 101      */
 102     void sendResult(PacketPtr &pkt, MSHR* cshr, bool success)
 103     {
 104         //Don't do coherence
 105         return;
 106     }
 107
 108
 109     /**
 110      * Return the proper state given the current state and the bus response.
 111      * @param pkt The bus response.
 112      * @param current The current block state.
 113      * @return The new state.
 114      */
 115     CacheBlk::State getNewState(PacketPtr &pkt, CacheBlk::State current)
 116     {
 117         return protocol->getNewState(pkt, current);
 118     }
 119
 120     /**
 121      * Handle snooped bus requests.
 122      * @param pkt The snooped bus request.
 123      * @param blk The cache block corresponding to the request, if any.
 124      * @param mshr The MSHR corresponding to the request, if any.
 125      * @param new_state Return the new state for the block.
 126      */
 127     bool handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
 128                           CacheBlk::State &new_state)
 129     {
 130 //      assert(mshr == NULL);
 131 //Got rid of, there could be an MSHR, but it can't be in service
 132         if (blk != NULL)
 133         {
 134             if (pkt->cmd != Packet::Writeback) {
 135                 return protocol->handleBusRequest(cache, pkt, blk, mshr,
 136                                               new_state);
 137             }
 138             else { //It is a writeback, must be ownership protocol, just keep state
 139                 new_state = blk->status;
 140             }
 141         }
 142         return false;
 143     }
 144
 145     /**
 146      * Get the proper bus command for the given command and status.
 147      * @param cmd The request's command.
 148      * @param state The current state of the cache block.
 149      * @return The proper bus command, as determined by the protocol.
 150      */
 151     Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state)
 152     {
 153         if (cmd == Packet::Writeback) return Packet::Writeback;
 154         return protocol->getBusCmd(cmd, state);
 155     }
 156
 157     /**
 158      * Return true if this coherence policy can handle fast cache writes.
 159      */
 160     bool allowFastWrites() { return false; }
 161
 162     bool hasProtocol() { return true; }
 163
 164     void propogateInvalidate(PacketPtr pkt, bool isTiming)
 165     {
 166         //For now we do nothing, asssumes simple coherence is top level of cache
 167         return;
 168     }
 169 };
 170
 171 #endif //__SIMPLE_COHERENCE_HH__
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