Merge ktlim@zamp:./local/clean/tmp/test-regress
[gem5.git] / src / mem / cache / coherence / uni_coherence.cc
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31 #include "mem/cache/coherence/uni_coherence.hh"
32 #include "mem/cache/base_cache.hh"
33
34 #include "base/trace.hh"
35
36 using namespace std;
37
38 UniCoherence::UniCoherence()
39 : cshrs(50)
40 {
41 }
42
43 PacketPtr
44 UniCoherence::getPacket()
45 {
46 PacketPtr pkt = cshrs.getReq();
47 return pkt;
48 }
49
50 void
51 UniCoherence::sendResult(PacketPtr &pkt, MSHR* cshr, bool success)
52 {
53 if (success)
54 {
55 bool unblock = cshrs.isFull();
56 // cshrs.markInService(cshr);
57 cshrs.deallocate(cshr);
58 if (!cshrs.havePending()) {
59 cache->clearSlaveRequest(Request_Coherence);
60 }
61 if (unblock) {
62 //since CSHRs are always used as buffers, should always get rid of one
63 assert(!cshrs.isFull());
64 cache->clearBlocked(Blocked_Coherence);
65 }
66 }
67 }
68
69
70 /**
71 * @todo add support for returning slave requests, not doing them here.
72 */
73 bool
74 UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
75 CacheBlk::State &new_state)
76 {
77 new_state = 0;
78 if (pkt->isInvalidate()) {
79 DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n",
80 pkt->getAddr(), blk);
81 }
82 else if (blk) {
83 new_state = blk->status;
84 }
85 return false;
86 }
87
88 void
89 UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming)
90 {
91 if (pkt->isInvalidate()) {
92 if (isTiming) {
93 // Forward to other caches
94 PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
95 cshrs.allocate(tmp);
96 cache->setSlaveRequest(Request_Coherence, curTick);
97 if (cshrs.isFull())
98 cache->setBlockedForSnoop(Blocked_Coherence);
99 }
100 else {
101 PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
102 cache->cpuSidePort->sendAtomic(tmp);
103 delete tmp;
104 }
105 }
106 }