src/mem/cache/miss/blocking_buffer.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Declaration of a simple buffer for a blocking cache.
  34  */
  35
  36 #ifndef __BLOCKING_BUFFER_HH__
  37 #define __BLOCKING_BUFFER_HH__
  38
  39 #include <vector>
  40
  41 #include "mem/cache/miss/mshr.hh"
  42 #include "base/statistics.hh"
  43
  44 class BaseCache;
  45 class BasePrefetcher;
  46
  47 /**
  48  * Miss and writeback storage for a blocking cache.
  49  */
  50 class BlockingBuffer
  51 {
  52 protected:
  53     /** Miss storage. */
  54     MSHR miss;
  55     /** WB storage. */
  56     MSHR wb;
  57
  58     //Params
  59
  60     /** Allocate on write misses. */
  61     const bool writeAllocate;
  62
  63     /** Pointer to the parent cache. */
  64     BaseCache* cache;
  65
  66     BasePrefetcher* prefetcher;
  67
  68     /** Block size of the parent cache. */
  69     int blkSize;
  70
  71     // Statistics
  72     /**
  73      * @addtogroup CacheStatistics
  74      * @{
  75      */
  76     /** Number of blocks written back per thread. */
  77     Stats::Vector<> writebacks;
  78
  79     /**
  80      * @}
  81      */
  82
  83 public:
  84     /**
  85      * Builds and initializes this buffer.
  86      * @param write_allocate If true, treat write misses the same as reads.
  87      */
  88     BlockingBuffer(bool write_allocate)
  89         : writeAllocate(write_allocate)
  90     {
  91     }
  92
  93     /**
  94      * Register statistics for this object.
  95      * @param name The name of the parent cache.
  96      */
  97     void regStats(const std::string &name);
  98
  99     /**
 100      * Called by the parent cache to set the back pointer.
 101      * @param _cache A pointer to the parent cache.
 102      */
 103     void setCache(BaseCache *_cache);
 104
 105     void setPrefetcher(BasePrefetcher *_prefetcher);
 106
 107     /**
 108      * Handle a cache miss properly. Requests the bus and marks the cache as
 109      * blocked.
 110      * @param pkt The request that missed in the cache.
 111      * @param blk_size The block size of the cache.
 112      * @param time The time the miss is detected.
 113      */
 114     void handleMiss(PacketPtr &pkt, int blk_size, Tick time);
 115
 116     /**
 117      * Fetch the block for the given address and buffer the given target.
 118      * @param addr The address to fetch.
 119      * @param asid The address space of the address.
 120      * @param blk_size The block size of the cache.
 121      * @param time The time the miss is detected.
 122      * @param target The target for the fetch.
 123      */
 124     MSHR* fetchBlock(Addr addr, int blk_size, Tick time,
 125                      PacketPtr &target)
 126     {
 127         fatal("Unimplemented");
 128     }
 129
 130     /**
 131      * Selects a outstanding request to service.
 132      * @return The request to service, NULL if none found.
 133      */
 134     PacketPtr getPacket();
 135
 136     /**
 137      * Set the command to the given bus command.
 138      * @param pkt The request to update.
 139      * @param cmd The bus command to use.
 140      */
 141     void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
 142
 143     /**
 144      * Restore the original command in case of a bus transmission error.
 145      * @param pkt The request to reset.
 146      */
 147     void restoreOrigCmd(PacketPtr &pkt);
 148
 149     /**
 150      * Marks a request as in service (sent on the bus). This can have side
 151      * effect since storage for no response commands is deallocated once they
 152      * are successfully sent.
 153      * @param pkt The request that was sent on the bus.
 154      */
 155     void markInService(PacketPtr &pkt, MSHR* mshr);
 156
 157     /**
 158      * Frees the resources of the request and unblock the cache.
 159      * @param pkt The request that has been satisfied.
 160      * @param time The time when the request is satisfied.
 161      */
 162     void handleResponse(PacketPtr &pkt, Tick time);
 163
 164     /**
 165      * Removes all outstanding requests for a given thread number. If a request
 166      * has been sent to the bus, this function removes all of its targets.
 167      * @param threadNum The thread number of the requests to squash.
 168      */
 169     void squash(int threadNum);
 170
 171     /**
 172      * Return the current number of outstanding misses.
 173      * @return the number of outstanding misses.
 174      */
 175     int getMisses()
 176     {
 177         return miss.getNumTargets();
 178     }
 179
 180     /**
 181      * Searches for the supplied address in the miss "queue".
 182      * @param addr The address to look for.
 183      * @param asid The address space id.
 184      * @return A pointer to miss if it matches.
 185      */
 186     MSHR* findMSHR(Addr addr)
 187     {
 188         if (miss.addr == addr && miss.pkt)
 189             return &miss;
 190         return NULL;
 191     }
 192
 193     /**
 194      * Searches for the supplied address in the write buffer.
 195      * @param addr The address to look for.
 196      * @param asid The address space id.
 197      * @param writes List of pointers to the matching writes.
 198      * @return True if there is a matching write.
 199      */
 200     bool findWrites(Addr addr, std::vector<MSHR*>& writes)
 201     {
 202         if (wb.addr == addr && wb.pkt) {
 203             writes.push_back(&wb);
 204             return true;
 205         }
 206         return false;
 207     }
 208
 209
 210
 211     /**
 212      * Perform a writeback of dirty data to the given address.
 213      * @param addr The address to write to.
 214      * @param asid The address space id.
 215      * @param size The number of bytes to write.
 216      * @param data The data to write, can be NULL.
 217      * @param compressed True if the data is compressed.
 218      */
 219     void doWriteback(Addr addr,
 220                      int size, uint8_t *data, bool compressed);
 221
 222     /**
 223      * Perform a writeback request.
 224      * @param pkt The writeback request.
 225      */
 226     void doWriteback(PacketPtr &pkt);
 227
 228     /**
 229      * Returns true if there are outstanding requests.
 230      * @return True if there are outstanding requests.
 231      */
 232     bool havePending()
 233     {
 234         return !miss.inService || !wb.inService;
 235     }
 236
 237     /**
 238      * Add a target to the given MSHR. This assumes it is in the miss queue.
 239      * @param mshr The mshr to add a target to.
 240      * @param pkt The target to add.
 241      */
 242     void addTarget(MSHR *mshr, PacketPtr &pkt)
 243     {
 244         fatal("Shouldn't call this on a blocking buffer.");
 245     }
 246
 247     /**
 248      * Dummy implmentation.
 249      */
 250     MSHR* allocateTargetList(Addr addr)
 251     {
 252         fatal("Unimplemented");
 253     }
 254 };
 255
 256 #endif // __BLOCKING_BUFFER_HH__