src/mem/cache/miss/miss_queue.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Erik Hallnor
  29  */
  30
  31 /**
  32  * @file
  33  * Miss and writeback queue declarations.
  34  */
  35
  36 #ifndef __MISS_QUEUE_HH__
  37 #define __MISS_QUEUE_HH__
  38
  39 #include <vector>
  40
  41 #include "mem/cache/miss/mshr.hh"
  42 #include "mem/cache/miss/mshr_queue.hh"
  43 #include "base/statistics.hh"
  44
  45 class BaseCache;
  46 class BasePrefetcher;
  47 /**
  48  * Manages cache misses and writebacks. Contains MSHRs to store miss data
  49  * and the writebuffer for writes/writebacks.
  50  * @todo need to handle data on writes better (encapsulate).
  51  * @todo need to make replacements/writebacks happen in Cache::access
  52  */
  53 class MissQueue
  54 {
  55   protected:
  56     /** The MSHRs. */
  57     MSHRQueue mq;
  58     /** Write Buffer. */
  59     MSHRQueue wb;
  60
  61     // PARAMTERS
  62
  63     /** The number of MSHRs in the miss queue. */
  64     const int numMSHR;
  65     /** The number of targets for each MSHR. */
  66     const int numTarget;
  67     /** The number of write buffers. */
  68     const int writeBuffers;
  69     /** True if the cache should allocate on a write miss. */
  70     const bool writeAllocate;
  71     /** Pointer to the parent cache. */
  72     BaseCache* cache;
  73
  74     /** The Prefetcher */
  75     BasePrefetcher *prefetcher;
  76
  77     /** The block size of the parent cache. */
  78     int blkSize;
  79
  80     /** Increasing order number assigned to each incoming request. */
  81     uint64_t order;
  82
  83     bool prefetchMiss;
  84
  85     // Statistics
  86     /**
  87      * @addtogroup CacheStatistics
  88      * @{
  89      */
  90     /** Number of blocks written back per thread. */
  91     Stats::Vector<> writebacks;
  92
  93     /** Number of misses that hit in the MSHRs per command and thread. */
  94     Stats::Vector<> mshr_hits[NUM_MEM_CMDS];
  95     /** Demand misses that hit in the MSHRs. */
  96     Stats::Formula demandMshrHits;
  97     /** Total number of misses that hit in the MSHRs. */
  98     Stats::Formula overallMshrHits;
  99
 100     /** Number of misses that miss in the MSHRs, per command and thread. */
 101     Stats::Vector<> mshr_misses[NUM_MEM_CMDS];
 102     /** Demand misses that miss in the MSHRs. */
 103     Stats::Formula demandMshrMisses;
 104     /** Total number of misses that miss in the MSHRs. */
 105     Stats::Formula overallMshrMisses;
 106
 107     /** Number of misses that miss in the MSHRs, per command and thread. */
 108     Stats::Vector<> mshr_uncacheable[NUM_MEM_CMDS];
 109     /** Total number of misses that miss in the MSHRs. */
 110     Stats::Formula overallMshrUncacheable;
 111
 112     /** Total cycle latency of each MSHR miss, per command and thread. */
 113     Stats::Vector<> mshr_miss_latency[NUM_MEM_CMDS];
 114     /** Total cycle latency of demand MSHR misses. */
 115     Stats::Formula demandMshrMissLatency;
 116     /** Total cycle latency of overall MSHR misses. */
 117     Stats::Formula overallMshrMissLatency;
 118
 119     /** Total cycle latency of each MSHR miss, per command and thread. */
 120     Stats::Vector<> mshr_uncacheable_lat[NUM_MEM_CMDS];
 121     /** Total cycle latency of overall MSHR misses. */
 122     Stats::Formula overallMshrUncacheableLatency;
 123
 124     /** The total number of MSHR accesses per command and thread. */
 125     Stats::Formula mshrAccesses[NUM_MEM_CMDS];
 126     /** The total number of demand MSHR accesses. */
 127     Stats::Formula demandMshrAccesses;
 128     /** The total number of MSHR accesses. */
 129     Stats::Formula overallMshrAccesses;
 130
 131     /** The miss rate in the MSHRs pre command and thread. */
 132     Stats::Formula mshrMissRate[NUM_MEM_CMDS];
 133     /** The demand miss rate in the MSHRs. */
 134     Stats::Formula demandMshrMissRate;
 135     /** The overall miss rate in the MSHRs. */
 136     Stats::Formula overallMshrMissRate;
 137
 138     /** The average latency of an MSHR miss, per command and thread. */
 139     Stats::Formula avgMshrMissLatency[NUM_MEM_CMDS];
 140     /** The average latency of a demand MSHR miss. */
 141     Stats::Formula demandAvgMshrMissLatency;
 142     /** The average overall latency of an MSHR miss. */
 143     Stats::Formula overallAvgMshrMissLatency;
 144
 145     /** The average latency of an MSHR miss, per command and thread. */
 146     Stats::Formula avgMshrUncacheableLatency[NUM_MEM_CMDS];
 147     /** The average overall latency of an MSHR miss. */
 148     Stats::Formula overallAvgMshrUncacheableLatency;
 149
 150     /** The number of times a thread hit its MSHR cap. */
 151     Stats::Vector<> mshr_cap_events;
 152     /** The number of times software prefetches caused the MSHR to block. */
 153     Stats::Vector<> soft_prefetch_mshr_full;
 154
 155     Stats::Scalar<> mshr_no_allocate_misses;
 156
 157     /**
 158      * @}
 159      */
 160
 161   private:
 162     /** Pointer to the MSHR that has no targets. */
 163     MSHR* noTargetMSHR;
 164
 165     /**
 166      * Allocate a new MSHR to handle the provided miss.
 167      * @param pkt The miss to buffer.
 168      * @param size The number of bytes to fetch.
 169      * @param time The time the miss occurs.
 170      * @return A pointer to the new MSHR.
 171      */
 172     MSHR* allocateMiss(PacketPtr &pkt, int size, Tick time);
 173
 174     /**
 175      * Allocate a new WriteBuffer to handle the provided write.
 176      * @param pkt The write to handle.
 177      * @param size The number of bytes to write.
 178      * @param time The time the write occurs.
 179      * @return A pointer to the new write buffer.
 180      */
 181     MSHR* allocateWrite(PacketPtr &pkt, int size, Tick time);
 182
 183   public:
 184     /**
 185      * Simple Constructor. Initializes all needed internal storage and sets
 186      * parameters.
 187      * @param numMSHRs The number of outstanding misses to handle.
 188      * @param numTargets The number of outstanding targets to each miss.
 189      * @param write_buffers The number of outstanding writes to handle.
 190      * @param write_allocate If true, treat write misses the same as reads.
 191      */
 192     MissQueue(int numMSHRs, int numTargets, int write_buffers,
 193               bool write_allocate, bool prefetch_miss);
 194
 195     /**
 196      * Deletes all allocated internal storage.
 197      */
 198     ~MissQueue();
 199
 200     /**
 201      * Register statistics for this object.
 202      * @param name The name of the parent cache.
 203      */
 204     void regStats(const std::string &name);
 205
 206     /**
 207      * Called by the parent cache to set the back pointer.
 208      * @param _cache A pointer to the parent cache.
 209      */
 210     void setCache(BaseCache *_cache);
 211
 212     void setPrefetcher(BasePrefetcher *_prefetcher);
 213
 214     /**
 215      * Handle a cache miss properly. Either allocate an MSHR for the request,
 216      * or forward it through the write buffer.
 217      * @param pkt The request that missed in the cache.
 218      * @param blk_size The block size of the cache.
 219      * @param time The time the miss is detected.
 220      */
 221     void handleMiss(PacketPtr &pkt, int blk_size, Tick time);
 222
 223     /**
 224      * Fetch the block for the given address and buffer the given target.
 225      * @param addr The address to fetch.
 226      * @param asid The address space of the address.
 227      * @param blk_size The block size of the cache.
 228      * @param time The time the miss is detected.
 229      * @param target The target for the fetch.
 230      */
 231     MSHR* fetchBlock(Addr addr, int blk_size, Tick time,
 232                      PacketPtr &target);
 233
 234     /**
 235      * Selects a outstanding request to service.
 236      * @return The request to service, NULL if none found.
 237      */
 238     PacketPtr getPacket();
 239
 240     /**
 241      * Set the command to the given bus command.
 242      * @param pkt The request to update.
 243      * @param cmd The bus command to use.
 244      */
 245     void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
 246
 247     /**
 248      * Restore the original command in case of a bus transmission error.
 249      * @param pkt The request to reset.
 250      */
 251     void restoreOrigCmd(PacketPtr &pkt);
 252
 253     /**
 254      * Marks a request as in service (sent on the bus). This can have side
 255      * effect since storage for no response commands is deallocated once they
 256      * are successfully sent.
 257      * @param pkt The request that was sent on the bus.
 258      */
 259     void markInService(PacketPtr &pkt, MSHR* mshr);
 260
 261     /**
 262      * Collect statistics and free resources of a satisfied request.
 263      * @param pkt The request that has been satisfied.
 264      * @param time The time when the request is satisfied.
 265      */
 266     void handleResponse(PacketPtr &pkt, Tick time);
 267
 268     /**
 269      * Removes all outstanding requests for a given thread number. If a request
 270      * has been sent to the bus, this function removes all of its targets.
 271      * @param threadNum The thread number of the requests to squash.
 272      */
 273     void squash(int threadNum);
 274
 275     /**
 276      * Return the current number of outstanding misses.
 277      * @return the number of outstanding misses.
 278      */
 279     int getMisses()
 280     {
 281         return mq.getAllocatedTargets();
 282     }
 283
 284     /**
 285      * Searches for the supplied address in the miss queue.
 286      * @param addr The address to look for.
 287      * @param asid The address space id.
 288      * @return The MSHR that contains the address, NULL if not found.
 289      * @warning Currently only searches the miss queue. If non write allocate
 290      * might need to search the write buffer for coherence.
 291      */
 292     MSHR* findMSHR(Addr addr) const;
 293
 294     /**
 295      * Searches for the supplied address in the write buffer.
 296      * @param addr The address to look for.
 297      * @param asid The address space id.
 298      * @param writes The list of writes that match the address.
 299      * @return True if any writes are found
 300      */
 301     bool findWrites(Addr addr, std::vector<MSHR*>& writes) const;
 302
 303     /**
 304      * Perform a writeback of dirty data to the given address.
 305      * @param addr The address to write to.
 306      * @param asid The address space id.
 307      * @param xc The execution context of the address space.
 308      * @param size The number of bytes to write.
 309      * @param data The data to write, can be NULL.
 310      * @param compressed True if the data is compressed.
 311      */
 312     void doWriteback(Addr addr,
 313                      int size, uint8_t *data, bool compressed);
 314
 315     /**
 316      * Perform the given writeback request.
 317      * @param pkt The writeback request.
 318      */
 319     void doWriteback(PacketPtr &pkt);
 320
 321     /**
 322      * Returns true if there are outstanding requests.
 323      * @return True if there are outstanding requests.
 324      */
 325     bool havePending();
 326
 327     /**
 328      * Add a target to the given MSHR. This assumes it is in the miss queue.
 329      * @param mshr The mshr to add a target to.
 330      * @param pkt The target to add.
 331      */
 332     void addTarget(MSHR *mshr, PacketPtr &pkt)
 333     {
 334         mq.allocateTarget(mshr, pkt);
 335     }
 336
 337     /**
 338      * Allocate a MSHR to hold a list of targets to a block involved in a copy.
 339      * If the block is marked done then the MSHR already holds the data to
 340      * fill the block. Otherwise the block needs to be fetched.
 341      * @param addr The address to buffer.
 342      * @param asid The address space ID.
 343      * @return A pointer to the allocated MSHR.
 344      */
 345     MSHR* allocateTargetList(Addr addr);
 346
 347 };
 348
 349 #endif //__MISS_QUEUE_HH__