src/mem/cache/mshr.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Nikos Nikoleris
  42  */
  43
  44 /**
  45  * @file
  46  * Miss Status and Handling Register (MSHR) declaration.
  47  */
  48
  49 #ifndef __MEM_CACHE_MSHR_HH__
  50 #define __MEM_CACHE_MSHR_HH__
  51
  52 #include <cassert>
  53 #include <iosfwd>
  54 #include <list>
  55 #include <string>
  56 #include <vector>
  57
  58 #include "base/printable.hh"
  59 #include "base/types.hh"
  60 #include "mem/cache/queue_entry.hh"
  61 #include "mem/packet.hh"
  62 #include "mem/request.hh"
  63 #include "sim/core.hh"
  64
  65 class BaseCache;
  66
  67 /**
  68  * Miss Status and handling Register. This class keeps all the information
  69  * needed to handle a cache miss including a list of target requests.
  70  * @sa  \ref gem5MemorySystem "gem5 Memory System"
  71  */
  72 class MSHR : public QueueEntry, public Printable
  73 {
  74
  75     /**
  76      * Consider the queues friends to avoid making everything public.
  77      */
  78     template<typename Entry>
  79     friend class Queue;
  80     friend class MSHRQueue;
  81
  82   private:
  83
  84     /** Flag set by downstream caches */
  85     bool downstreamPending;
  86
  87     /**
  88      * Here we use one flag to track both if:
  89      *
  90      * 1. We are going to become owner or not, i.e., we will get the
  91      * block in an ownership state (Owned or Modified) with BlkDirty
  92      * set. This determines whether or not we are going to become the
  93      * responder and ordering point for future requests that we snoop.
  94      *
  95      * 2. We know that we are going to get a writable block, i.e. we
  96      * will get the block in writable state (Exclusive or Modified
  97      * state) with BlkWritable set. That determines whether additional
  98      * targets with needsWritable set will be able to be satisfied, or
  99      * if not should be put on the deferred list to possibly wait for
 100      * another request that does give us writable access.
 101      *
 102      * Condition 2 is actually just a shortcut that saves us from
 103      * possibly building a deferred target list and calling
 104      * promoteWritable() every time we get a writable block. Condition
 105      * 1, tracking ownership, is what is important. However, we never
 106      * receive ownership without marking the block dirty, and
 107      * consequently use pendingModified to track both ownership and
 108      * writability rather than having separate pendingDirty and
 109      * pendingWritable flags.
 110      */
 111     bool pendingModified;
 112
 113     /** Did we snoop an invalidate while waiting for data? */
 114     bool postInvalidate;
 115
 116     /** Did we snoop a read while waiting for data? */
 117     bool postDowngrade;
 118
 119   public:
 120
 121     /** Track if we sent this as a whole line write or not */
 122     bool wasWholeLineWrite;
 123
 124     /** True if the entry is just a simple forward from an upper level */
 125     bool isForward;
 126
 127     class Target : public QueueEntry::Target {
 128       public:
 129
 130         enum Source {
 131             FromCPU,
 132             FromSnoop,
 133             FromPrefetcher
 134         };
 135
 136         const Source source;  //!< Request from cpu, memory, or prefetcher?
 137
 138         /**
 139          * We use this flag to track whether we have cleared the
 140          * downstreamPending flag for the MSHR of the cache above
 141          * where this packet originates from and guard noninitial
 142          * attempts to clear it.
 143          *
 144          * The flag markedPending needs to be updated when the
 145          * TargetList is in service which can be:
 146          * 1) during the Target instantiation if the MSHR is in
 147          * service and the target is not deferred,
 148          * 2) when the MSHR becomes in service if the target is not
 149          * deferred,
 150          * 3) or when the TargetList is promoted (deferredTargets ->
 151          * targets).
 152          */
 153         bool markedPending;
 154
 155         const bool allocOnFill;   //!< Should the response servicing this
 156                                   //!< target list allocate in the cache?
 157
 158         Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
 159                Source _source, bool _markedPending, bool alloc_on_fill)
 160             : QueueEntry::Target(_pkt, _readyTime, _order), source(_source),
 161               markedPending(_markedPending), allocOnFill(alloc_on_fill)
 162         {}
 163     };
 164
 165     class TargetList : public std::list<Target> {
 166
 167       public:
 168         bool needsWritable;
 169         bool hasUpgrade;
 170         /** Set when the response should allocate on fill */
 171         bool allocOnFill;
 172         /**
 173          * Determine whether there was at least one non-snooping
 174          * target coming from another cache.
 175          */
 176         bool hasFromCache;
 177
 178         TargetList();
 179
 180         /**
 181          * Use the provided packet and the source to update the
 182          * flags of this TargetList.
 183          *
 184          * @param pkt Packet considered for the flag update
 185          * @param source Indicates the source of the packet
 186          * @param alloc_on_fill Whether the pkt would allocate on a fill
 187          */
 188         void updateFlags(PacketPtr pkt, Target::Source source,
 189                          bool alloc_on_fill);
 190
 191         /**
 192          * Reset state
 193          *
 194          * @param blk_addr Address of the cache block
 195          * @param blk_size Size of the cache block
 196          */
 197         void init(Addr blk_addr, Addr blk_size) {
 198             blkAddr = blk_addr;
 199             blkSize = blk_size;
 200             writesBitmap.resize(blk_size);
 201
 202             resetFlags();
 203         }
 204
 205         void resetFlags() {
 206             canMergeWrites = true;
 207             std::fill(writesBitmap.begin(), writesBitmap.end(), false);
 208
 209             needsWritable = false;
 210             hasUpgrade = false;
 211             allocOnFill = false;
 212             hasFromCache = false;
 213         }
 214
 215         /**
 216          * Goes through the list of targets and uses them to populate
 217          * the flags of this TargetList. When the function returns the
 218          * flags are consistent with the properties of packets in the
 219          * list.
 220          */
 221         void populateFlags();
 222
 223         /**
 224          * Add the specified packet in the TargetList. This function
 225          * stores information related to the added packet and updates
 226          * accordingly the flags.
 227          *
 228          * @param pkt Packet considered for adding
 229          */
 230         void updateWriteFlags(PacketPtr pkt);
 231
 232         /**
 233          * Tests if the flags of this TargetList have their default
 234          * values.
 235          *
 236          * @return True if the TargetList are reset, false otherwise.
 237          */
 238         bool isReset() const {
 239             return !needsWritable && !hasUpgrade && !allocOnFill &&
 240                 !hasFromCache && canMergeWrites;
 241         }
 242
 243         /**
 244          * Add the specified packet in the TargetList. This function
 245          * stores information related to the added packet and updates
 246          * accordingly the flags.
 247          *
 248          * @param pkt Packet considered for adding
 249          * @param readTime Tick at which the packet is processed by this cache
 250          * @param order A counter giving a unique id to each target
 251          * @param source Indicates the source agent of the packet
 252          * @param markPending Set for deferred targets or pending MSHRs
 253          * @param alloc_on_fill Whether it should allocate on a fill
 254          */
 255         void add(PacketPtr pkt, Tick readyTime, Counter order,
 256                  Target::Source source, bool markPending, bool alloc_on_fill);
 257
 258         /**
 259          * Convert upgrades to the equivalent request if the cache line they
 260          * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
 261          * Used to rejig ordering between targets waiting on an MSHR. */
 262         void replaceUpgrades();
 263
 264         void clearDownstreamPending();
 265         void clearDownstreamPending(iterator begin, iterator end);
 266         bool trySatisfyFunctional(PacketPtr pkt);
 267         void print(std::ostream &os, int verbosity,
 268                    const std::string &prefix) const;
 269
 270         /**
 271          * Check if this list contains writes that cover an entire
 272          * cache line. This is used as part of the miss-packet
 273          * creation. Note that new requests may arrive after a
 274          * miss-packet has been created, and for the corresponding
 275          * fill we use the wasWholeLineWrite field.
 276          */
 277         bool isWholeLineWrite() const
 278         {
 279             return std::all_of(writesBitmap.begin(), writesBitmap.end(),
 280                                [](bool i) { return i; });
 281         }
 282
 283       private:
 284         /** Address of the cache block for this list of targets. */
 285         Addr blkAddr;
 286
 287         /** Size of the cache block. */
 288         Addr blkSize;
 289
 290         /** Indicates whether we can merge incoming write requests */
 291         bool canMergeWrites;
 292
 293         // NOTE: std::vector<bool> might not meet satisfy the
 294         // ForwardIterator requirement and therefore cannot be used
 295         // for writesBitmap.
 296         /**
 297          * Track which bytes are written by requests in this target
 298          * list.
 299          */
 300         std::vector<char> writesBitmap;
 301     };
 302
 303     /** A list of MSHRs. */
 304     typedef std::list<MSHR *> List;
 305     /** MSHR list iterator. */
 306     typedef List::iterator Iterator;
 307
 308     /** The pending* and post* flags are only valid if inService is
 309      *  true.  Using the accessor functions lets us detect if these
 310      *  flags are accessed improperly.
 311      */
 312
 313     /** True if we need to get a writable copy of the block. */
 314     bool needsWritable() const { return targets.needsWritable; }
 315
 316     bool isCleaning() const {
 317         PacketPtr pkt = targets.front().pkt;
 318         return pkt->isClean();
 319     }
 320
 321     bool isPendingModified() const {
 322         assert(inService); return pendingModified;
 323     }
 324
 325     bool hasPostInvalidate() const {
 326         assert(inService); return postInvalidate;
 327     }
 328
 329     bool hasPostDowngrade() const {
 330         assert(inService); return postDowngrade;
 331     }
 332
 333     bool sendPacket(BaseCache &cache) override;
 334
 335     bool allocOnFill() const {
 336         return targets.allocOnFill;
 337     }
 338
 339     /**
 340      * Determine if there are non-deferred requests from other caches
 341      *
 342      * @return true if any of the targets is from another cache
 343      */
 344     bool hasFromCache() const {
 345         return targets.hasFromCache;
 346     }
 347
 348   private:
 349     /**
 350      * Promotes deferred targets that satisfy a predicate
 351      *
 352      * Deferred targets are promoted to the target list if they
 353      * satisfy a given condition. The operation stops at the first
 354      * deferred target that doesn't satisfy the condition.
 355      *
 356      * @param pred A condition on a Target
 357      */
 358     void promoteIf(const std::function<bool (Target &)>& pred);
 359
 360     /**
 361      * Pointer to this MSHR on the ready list.
 362      * @sa MissQueue, MSHRQueue::readyList
 363      */
 364     Iterator readyIter;
 365
 366     /**
 367      * Pointer to this MSHR on the allocated list.
 368      * @sa MissQueue, MSHRQueue::allocatedList
 369      */
 370     Iterator allocIter;
 371
 372     /** List of all requests that match the address */
 373     TargetList targets;
 374
 375     TargetList deferredTargets;
 376
 377   public:
 378     /**
 379      * Check if this MSHR contains only compatible writes, and if they
 380      * span the entire cache line. This is used as part of the
 381      * miss-packet creation. Note that new requests may arrive after a
 382      * miss-packet has been created, and for the fill we therefore use
 383      * the wasWholeLineWrite field.
 384      */
 385     bool isWholeLineWrite() const {
 386         return targets.isWholeLineWrite();
 387     }
 388
 389     /**
 390      * Allocate a miss to this MSHR.
 391      * @param blk_addr The address of the block.
 392      * @param blk_size The number of bytes to request.
 393      * @param pkt The original miss.
 394      * @param when_ready When should the MSHR be ready to act upon.
 395      * @param _order The logical order of this MSHR
 396      * @param alloc_on_fill Should the cache allocate a block on fill
 397      */
 398     void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
 399                   Tick when_ready, Counter _order, bool alloc_on_fill);
 400
 401     void markInService(bool pending_modified_resp);
 402
 403     void clearDownstreamPending();
 404
 405     /**
 406      * Mark this MSHR as free.
 407      */
 408     void deallocate();
 409
 410     /**
 411      * Add a request to the list of targets.
 412      * @param target The target.
 413      */
 414     void allocateTarget(PacketPtr target, Tick when, Counter order,
 415                         bool alloc_on_fill);
 416     bool handleSnoop(PacketPtr target, Counter order);
 417
 418     /** A simple constructor. */
 419     MSHR();
 420
 421     /**
 422      * Returns the current number of allocated targets.
 423      * @return The current number of allocated targets.
 424      */
 425     int getNumTargets() const
 426     { return targets.size() + deferredTargets.size(); }
 427
 428     /**
 429      * Extracts the subset of the targets that can be serviced given a
 430      * received response. This function returns the targets list
 431      * unless the response is a ReadRespWithInvalidate. The
 432      * ReadRespWithInvalidate is only invalidating response that its
 433      * invalidation was not expected when the request (a
 434      * ReadSharedReq) was sent out. For ReadRespWithInvalidate we can
 435      * safely service only the first FromCPU target and all FromSnoop
 436      * targets (inform all snoopers that we no longer have the block).
 437      *
 438      * @param pkt The response from the downstream memory
 439      */
 440     TargetList extractServiceableTargets(PacketPtr pkt);
 441
 442     /**
 443      * Returns true if there are targets left.
 444      * @return true if there are targets
 445      */
 446     bool hasTargets() const { return !targets.empty(); }
 447
 448     /**
 449      * Returns a reference to the first target.
 450      * @return A pointer to the first target.
 451      */
 452     QueueEntry::Target *getTarget() override
 453     {
 454         assert(hasTargets());
 455         return &targets.front();
 456     }
 457
 458     /**
 459      * Pop first target.
 460      */
 461     void popTarget()
 462     {
 463         targets.pop_front();
 464     }
 465
 466     bool promoteDeferredTargets();
 467
 468     /**
 469      * Promotes deferred targets that do not require writable
 470      *
 471      * Move targets from the deferred targets list to the target list
 472      * starting from the first deferred target until the first target
 473      * that is a cache maintenance operation or needs a writable copy
 474      * of the block
 475      */
 476     void promoteReadable();
 477
 478     /**
 479      * Promotes deferred targets that do not require writable
 480      *
 481      * Requests in the deferred target list are moved to the target
 482      * list up until the first target that is a cache maintenance
 483      * operation or needs a writable copy of the block
 484      */
 485     void promoteWritable();
 486
 487     bool trySatisfyFunctional(PacketPtr pkt);
 488
 489     /**
 490      * Adds a delay relative to the current tick to the current MSHR
 491      * @param delay_ticks the desired delay in ticks
 492      */
 493     void delay(Tick delay_ticks)
 494     {
 495         assert(readyTime <= curTick());
 496         readyTime = curTick() + delay_ticks;
 497     }
 498
 499     /**
 500      * Prints the contents of this MSHR for debugging.
 501      */
 502     void print(std::ostream &os,
 503                int verbosity = 0,
 504                const std::string &prefix = "") const override;
 505     /**
 506      * A no-args wrapper of print(std::ostream...)  meant to be
 507      * invoked from DPRINTFs avoiding string overheads in fast mode
 508      *
 509      * @return string with mshr fields + [deferred]targets
 510      */
 511     std::string print() const;
 512
 513     bool matchBlockAddr(const Addr addr, const bool is_secure) const override;
 514     bool matchBlockAddr(const PacketPtr pkt) const override;
 515     bool conflictAddr(const QueueEntry* entry) const override;
 516 };
 517
 518 #endif // __MEM_CACHE_MSHR_HH__