c7ddcda1c2d1bcdcbe2c790d9ed0428da65d0aee
[gem5.git] / src / mem / cache / prefetch / Prefetcher.py
1 # Copyright (c) 2012, 2014, 2019 ARM Limited
2 # All rights reserved.
3 #
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
12 #
13 # Copyright (c) 2005 The Regents of The University of Michigan
14 # All rights reserved.
15 #
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
26 #
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #
39 # Authors: Ron Dreslinski
40 # Mitch Hayenga
41
42 from m5.SimObject import *
43 from m5.params import *
44 from m5.proxy import *
45
46 from m5.objects.ClockedObject import ClockedObject
47 from m5.objects.IndexingPolicies import *
48 from m5.objects.ReplacementPolicies import *
49
50 class HWPProbeEvent(object):
51 def __init__(self, prefetcher, obj, *listOfNames):
52 self.obj = obj
53 self.prefetcher = prefetcher
54 self.names = listOfNames
55
56 def register(self):
57 if self.obj:
58 for name in self.names:
59 self.prefetcher.getCCObject().addEventProbe(
60 self.obj.getCCObject(), name)
61
62 class BasePrefetcher(ClockedObject):
63 type = 'BasePrefetcher'
64 abstract = True
65 cxx_header = "mem/cache/prefetch/base.hh"
66 cxx_exports = [
67 PyBindMethod("addEventProbe"),
68 PyBindMethod("addTLB"),
69 ]
70 sys = Param.System(Parent.any, "System this prefetcher belongs to")
71
72 # Get the block size from the parent (system)
73 block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
74
75 on_miss = Param.Bool(False, "Only notify prefetcher on misses")
76 on_read = Param.Bool(True, "Notify prefetcher on reads")
77 on_write = Param.Bool(True, "Notify prefetcher on writes")
78 on_data = Param.Bool(True, "Notify prefetcher on data accesses")
79 on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses")
80 prefetch_on_access = Param.Bool(Parent.prefetch_on_access,
81 "Notify the hardware prefetcher on every access (not just misses)")
82 use_virtual_addresses = Param.Bool(False,
83 "Use virtual addresses for prefetching")
84
85 _events = []
86 def addEvent(self, newObject):
87 self._events.append(newObject)
88
89 # Override the normal SimObject::regProbeListeners method and
90 # register deferred event handlers.
91 def regProbeListeners(self):
92 for tlb in self._tlbs:
93 self.getCCObject().addTLB(tlb.getCCObject())
94 for event in self._events:
95 event.register()
96 self.getCCObject().regProbeListeners()
97
98 def listenFromProbe(self, simObj, *probeNames):
99 if not isinstance(simObj, SimObject):
100 raise TypeError("argument must be of SimObject type")
101 if len(probeNames) <= 0:
102 raise TypeError("probeNames must have at least one element")
103 self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
104 _tlbs = []
105 def registerTLB(self, simObj):
106 if not isinstance(simObj, SimObject):
107 raise TypeError("argument must be a SimObject type")
108 self._tlbs.append(simObj)
109
110 class MultiPrefetcher(BasePrefetcher):
111 type = 'MultiPrefetcher'
112 cxx_class = 'MultiPrefetcher'
113 cxx_header = 'mem/cache/prefetch/multi.hh'
114
115 prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers")
116
117 class QueuedPrefetcher(BasePrefetcher):
118 type = "QueuedPrefetcher"
119 abstract = True
120 cxx_class = "QueuedPrefetcher"
121 cxx_header = "mem/cache/prefetch/queued.hh"
122 latency = Param.Int(1, "Latency for generated prefetches")
123 queue_size = Param.Int(32, "Maximum number of queued prefetches")
124 max_prefetch_requests_with_pending_translation = Param.Int(32,
125 "Maximum number of queued prefetches that have a missing translation")
126 queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
127 queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
128 cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
129
130 tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
131
132 # The throttle_control_percentage controls how many of the candidate
133 # addresses generated by the prefetcher will be finally turned into
134 # prefetch requests
135 # - If set to 100, all candidates can be discarded (one request
136 # will always be allowed to be generated)
137 # - Setting it to 0 will disable the throttle control, so requests are
138 # created for all candidates
139 # - If set to 60, 40% of candidates will generate a request, and the
140 # remaining 60% will be generated depending on the current accuracy
141 throttle_control_percentage = Param.Percent(0, "Percentage of requests \
142 that can be throttled depending on the accuracy of the prefetcher.")
143
144 class StridePrefetcher(QueuedPrefetcher):
145 type = 'StridePrefetcher'
146 cxx_class = 'StridePrefetcher'
147 cxx_header = "mem/cache/prefetch/stride.hh"
148
149 # Do not consult stride prefetcher on instruction accesses
150 on_inst = False
151
152 max_conf = Param.Int(7, "Maximum confidence level")
153 thresh_conf = Param.Int(4, "Threshold confidence level")
154 min_conf = Param.Int(0, "Minimum confidence level")
155 start_conf = Param.Int(4, "Starting confidence for new entries")
156
157 table_sets = Param.Int(16, "Number of sets in PC lookup table")
158 table_assoc = Param.Int(4, "Associativity of PC lookup table")
159 use_master_id = Param.Bool(True, "Use master id based history")
160
161 degree = Param.Int(4, "Number of prefetches to generate")
162
163 # Get replacement policy
164 replacement_policy = Param.BaseReplacementPolicy(RandomRP(),
165 "Replacement policy")
166
167 class TaggedPrefetcher(QueuedPrefetcher):
168 type = 'TaggedPrefetcher'
169 cxx_class = 'TaggedPrefetcher'
170 cxx_header = "mem/cache/prefetch/tagged.hh"
171
172 degree = Param.Int(2, "Number of prefetches to generate")
173
174 class IndirectMemoryPrefetcher(QueuedPrefetcher):
175 type = 'IndirectMemoryPrefetcher'
176 cxx_class = 'IndirectMemoryPrefetcher'
177 cxx_header = "mem/cache/prefetch/indirect_memory.hh"
178 pt_table_entries = Param.MemorySize("16",
179 "Number of entries of the Prefetch Table")
180 pt_table_assoc = Param.Unsigned(16, "Associativity of the Prefetch Table")
181 pt_table_indexing_policy = Param.BaseIndexingPolicy(
182 SetAssociative(entry_size = 1, assoc = Parent.pt_table_assoc,
183 size = Parent.pt_table_entries),
184 "Indexing policy of the pattern table")
185 pt_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
186 "Replacement policy of the pattern table")
187 max_prefetch_distance = Param.Unsigned(16, "Maximum prefetch distance")
188 num_indirect_counter_bits = Param.Unsigned(3,
189 "Number of bits of the indirect counter")
190 ipd_table_entries = Param.MemorySize("4",
191 "Number of entries of the Indirect Pattern Detector")
192 ipd_table_assoc = Param.Unsigned(4,
193 "Associativity of the Indirect Pattern Detector")
194 ipd_table_indexing_policy = Param.BaseIndexingPolicy(
195 SetAssociative(entry_size = 1, assoc = Parent.ipd_table_assoc,
196 size = Parent.ipd_table_entries),
197 "Indexing policy of the Indirect Pattern Detector")
198 ipd_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
199 "Replacement policy of the Indirect Pattern Detector")
200 shift_values = VectorParam.Int([2, 3, 4, -3], "Shift values to evaluate")
201 addr_array_len = Param.Unsigned(4, "Number of misses tracked")
202 prefetch_threshold = Param.Unsigned(2,
203 "Counter threshold to start the indirect prefetching")
204 stream_counter_threshold = Param.Unsigned(4,
205 "Counter threshold to enable the stream prefetcher")
206 streaming_distance = Param.Unsigned(4,
207 "Number of prefetches to generate when using the stream prefetcher")
208
209 class SignaturePathPrefetcher(QueuedPrefetcher):
210 type = 'SignaturePathPrefetcher'
211 cxx_class = 'SignaturePathPrefetcher'
212 cxx_header = "mem/cache/prefetch/signature_path.hh"
213
214 signature_shift = Param.UInt8(3,
215 "Number of bits to shift when calculating a new signature");
216 signature_bits = Param.UInt16(12,
217 "Size of the signature, in bits");
218 signature_table_entries = Param.MemorySize("1024",
219 "Number of entries of the signature table")
220 signature_table_assoc = Param.Unsigned(2,
221 "Associativity of the signature table")
222 signature_table_indexing_policy = Param.BaseIndexingPolicy(
223 SetAssociative(entry_size = 1, assoc = Parent.signature_table_assoc,
224 size = Parent.signature_table_entries),
225 "Indexing policy of the signature table")
226 signature_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
227 "Replacement policy of the signature table")
228
229 num_counter_bits = Param.UInt8(3,
230 "Number of bits of the saturating counters")
231 pattern_table_entries = Param.MemorySize("4096",
232 "Number of entries of the pattern table")
233 pattern_table_assoc = Param.Unsigned(1,
234 "Associativity of the pattern table")
235 strides_per_pattern_entry = Param.Unsigned(4,
236 "Number of strides stored in each pattern entry")
237 pattern_table_indexing_policy = Param.BaseIndexingPolicy(
238 SetAssociative(entry_size = 1, assoc = Parent.pattern_table_assoc,
239 size = Parent.pattern_table_entries),
240 "Indexing policy of the pattern table")
241 pattern_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
242 "Replacement policy of the pattern table")
243
244 prefetch_confidence_threshold = Param.Float(0.5,
245 "Minimum confidence to issue prefetches")
246 lookahead_confidence_threshold = Param.Float(0.75,
247 "Minimum confidence to continue exploring lookahead entries")
248
249 class SignaturePathPrefetcherV2(SignaturePathPrefetcher):
250 type = 'SignaturePathPrefetcherV2'
251 cxx_class = 'SignaturePathPrefetcherV2'
252 cxx_header = "mem/cache/prefetch/signature_path_v2.hh"
253
254 signature_table_entries = "256"
255 signature_table_assoc = 1
256 pattern_table_entries = "512"
257 pattern_table_assoc = 1
258 num_counter_bits = 4
259 prefetch_confidence_threshold = 0.25
260 lookahead_confidence_threshold = 0.25
261
262 global_history_register_entries = Param.MemorySize("8",
263 "Number of entries of global history register")
264 global_history_register_indexing_policy = Param.BaseIndexingPolicy(
265 SetAssociative(entry_size = 1,
266 assoc = Parent.global_history_register_entries,
267 size = Parent.global_history_register_entries),
268 "Indexing policy of the global history register")
269 global_history_register_replacement_policy = Param.BaseReplacementPolicy(
270 LRURP(), "Replacement policy of the global history register")
271
272 class AccessMapPatternMatching(ClockedObject):
273 type = 'AccessMapPatternMatching'
274 cxx_class = 'AccessMapPatternMatching'
275 cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
276
277 block_size = Param.Unsigned(Parent.block_size,
278 "Cacheline size used by the prefetcher using this object")
279
280 limit_stride = Param.Unsigned(0,
281 "Limit the strides checked up to -X/X, if 0, disable the limit")
282 start_degree = Param.Unsigned(4,
283 "Initial degree (Maximum number of prefetches generated")
284 hot_zone_size = Param.MemorySize("2kB", "Memory covered by a hot zone")
285 access_map_table_entries = Param.MemorySize("256",
286 "Number of entries in the access map table")
287 access_map_table_assoc = Param.Unsigned(8,
288 "Associativity of the access map table")
289 access_map_table_indexing_policy = Param.BaseIndexingPolicy(
290 SetAssociative(entry_size = 1, assoc = Parent.access_map_table_assoc,
291 size = Parent.access_map_table_entries),
292 "Indexing policy of the access map table")
293 access_map_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
294 "Replacement policy of the access map table")
295 high_coverage_threshold = Param.Float(0.25,
296 "A prefetch coverage factor bigger than this is considered high")
297 low_coverage_threshold = Param.Float(0.125,
298 "A prefetch coverage factor smaller than this is considered low")
299 high_accuracy_threshold = Param.Float(0.5,
300 "A prefetch accuracy factor bigger than this is considered high")
301 low_accuracy_threshold = Param.Float(0.25,
302 "A prefetch accuracy factor smaller than this is considered low")
303 high_cache_hit_threshold = Param.Float(0.875,
304 "A cache hit ratio bigger than this is considered high")
305 low_cache_hit_threshold = Param.Float(0.75,
306 "A cache hit ratio smaller than this is considered low")
307 epoch_cycles = Param.Cycles(256000, "Cycles in an epoch period")
308 offchip_memory_latency = Param.Latency("30ns",
309 "Memory latency used to compute the required memory bandwidth")
310
311 class AMPMPrefetcher(QueuedPrefetcher):
312 type = 'AMPMPrefetcher'
313 cxx_class = 'AMPMPrefetcher'
314 cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
315 ampm = Param.AccessMapPatternMatching( AccessMapPatternMatching(),
316 "Access Map Pattern Matching object")
317
318 class DeltaCorrelatingPredictionTables(SimObject):
319 type = 'DeltaCorrelatingPredictionTables'
320 cxx_class = 'DeltaCorrelatingPredictionTables'
321 cxx_header = "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
322 deltas_per_entry = Param.Unsigned(20,
323 "Number of deltas stored in each table entry")
324 delta_bits = Param.Unsigned(12, "Bits per delta")
325 delta_mask_bits = Param.Unsigned(8,
326 "Lower bits to mask when comparing deltas")
327 table_entries = Param.MemorySize("128",
328 "Number of entries in the table")
329 table_assoc = Param.Unsigned(128,
330 "Associativity of the table")
331 table_indexing_policy = Param.BaseIndexingPolicy(
332 SetAssociative(entry_size = 1, assoc = Parent.table_assoc,
333 size = Parent.table_entries),
334 "Indexing policy of the table")
335 table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
336 "Replacement policy of the table")
337
338 class DCPTPrefetcher(QueuedPrefetcher):
339 type = 'DCPTPrefetcher'
340 cxx_class = 'DCPTPrefetcher'
341 cxx_header = "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
342 dcpt = Param.DeltaCorrelatingPredictionTables(
343 DeltaCorrelatingPredictionTables(),
344 "Delta Correlating Prediction Tables object")
345
346 class IrregularStreamBufferPrefetcher(QueuedPrefetcher):
347 type = "IrregularStreamBufferPrefetcher"
348 cxx_class = "IrregularStreamBufferPrefetcher"
349 cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh"
350
351 num_counter_bits = Param.Unsigned(2,
352 "Number of bits of the confidence counter")
353 chunk_size = Param.Unsigned(256,
354 "Maximum number of addresses in a temporal stream")
355 degree = Param.Unsigned(4, "Number of prefetches to generate")
356 training_unit_assoc = Param.Unsigned(128,
357 "Associativity of the training unit")
358 training_unit_entries = Param.MemorySize("128",
359 "Number of entries of the training unit")
360 training_unit_indexing_policy = Param.BaseIndexingPolicy(
361 SetAssociative(entry_size = 1, assoc = Parent.training_unit_assoc,
362 size = Parent.training_unit_entries),
363 "Indexing policy of the training unit")
364 training_unit_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
365 "Replacement policy of the training unit")
366
367 prefetch_candidates_per_entry = Param.Unsigned(16,
368 "Number of prefetch candidates stored in a SP-AMC entry")
369 address_map_cache_assoc = Param.Unsigned(128,
370 "Associativity of the PS/SP AMCs")
371 address_map_cache_entries = Param.MemorySize("128",
372 "Number of entries of the PS/SP AMCs")
373 ps_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
374 SetAssociative(entry_size = 1,
375 assoc = Parent.address_map_cache_assoc,
376 size = Parent.address_map_cache_entries),
377 "Indexing policy of the Physical-to-Structural Address Map Cache")
378 ps_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
379 LRURP(),
380 "Replacement policy of the Physical-to-Structural Address Map Cache")
381 sp_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
382 SetAssociative(entry_size = 1,
383 assoc = Parent.address_map_cache_assoc,
384 size = Parent.address_map_cache_entries),
385 "Indexing policy of the Structural-to-Physical Address Mao Cache")
386 sp_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
387 LRURP(),
388 "Replacement policy of the Structural-to-Physical Address Map Cache")
389
390 class SlimAccessMapPatternMatching(AccessMapPatternMatching):
391 start_degree = 2
392 limit_stride = 4
393
394 class SlimDeltaCorrelatingPredictionTables(DeltaCorrelatingPredictionTables):
395 table_entries = "256"
396 table_assoc = 256
397 deltas_per_entry = 9
398
399 class SlimAMPMPrefetcher(QueuedPrefetcher):
400 type = 'SlimAMPMPrefetcher'
401 cxx_class = 'SlimAMPMPrefetcher'
402 cxx_header = "mem/cache/prefetch/slim_ampm.hh"
403
404 ampm = Param.AccessMapPatternMatching(SlimAccessMapPatternMatching(),
405 "Access Map Pattern Matching object")
406 dcpt = Param.DeltaCorrelatingPredictionTables(
407 SlimDeltaCorrelatingPredictionTables(),
408 "Delta Correlating Prediction Tables object")
409
410 class BOPPrefetcher(QueuedPrefetcher):
411 type = "BOPPrefetcher"
412 cxx_class = "BOPPrefetcher"
413 cxx_header = "mem/cache/prefetch/bop.hh"
414 score_max = Param.Unsigned(31, "Max. score to update the best offset")
415 round_max = Param.Unsigned(100, "Max. round to update the best offset")
416 bad_score = Param.Unsigned(10, "Score at which the HWP is disabled")
417 rr_size = Param.Unsigned(64, "Number of entries of each RR bank")
418 tag_bits = Param.Unsigned(12, "Bits used to store the tag")
419 offset_list_size = Param.Unsigned(46,
420 "Number of entries in the offsets list")
421 negative_offsets_enable = Param.Bool(True,
422 "Initialize the offsets list also with negative values \
423 (i.e. the table will have half of the entries with positive \
424 offsets and the other half with negative ones)")
425 delay_queue_enable = Param.Bool(True, "Enable the delay queue")
426 delay_queue_size = Param.Unsigned(15,
427 "Number of entries in the delay queue")
428 delay_queue_cycles = Param.Cycles(60,
429 "Cycles to delay a write in the left RR table from the delay \
430 queue")
431
432 class SBOOEPrefetcher(QueuedPrefetcher):
433 type = 'SBOOEPrefetcher'
434 cxx_class = 'SBOOEPrefetcher'
435 cxx_header = "mem/cache/prefetch/sbooe.hh"
436 latency_buffer_size = Param.Int(32, "Entries in the latency buffer")
437 sequential_prefetchers = Param.Int(9, "Number of sequential prefetchers")
438 sandbox_entries = Param.Int(1024, "Size of the address buffer")
439 score_threshold_pct = Param.Percent(25, "Min. threshold to issue a \
440 prefetch. The value is the percentage of sandbox entries to use")
441
442 class STeMSPrefetcher(QueuedPrefetcher):
443 type = "STeMSPrefetcher"
444 cxx_class = "STeMSPrefetcher"
445 cxx_header = "mem/cache/prefetch/spatio_temporal_memory_streaming.hh"
446
447 spatial_region_size = Param.MemorySize("2kB",
448 "Memory covered by a hot zone")
449 active_generation_table_entries = Param.MemorySize("64",
450 "Number of entries in the active generation table")
451 active_generation_table_assoc = Param.Unsigned(64,
452 "Associativity of the active generation table")
453 active_generation_table_indexing_policy = Param.BaseIndexingPolicy(
454 SetAssociative(entry_size = 1,
455 assoc = Parent.active_generation_table_assoc,
456 size = Parent.active_generation_table_entries),
457 "Indexing policy of the active generation table")
458 active_generation_table_replacement_policy = Param.BaseReplacementPolicy(
459 LRURP(), "Replacement policy of the active generation table")
460
461 pattern_sequence_table_entries = Param.MemorySize("16384",
462 "Number of entries in the pattern sequence table")
463 pattern_sequence_table_assoc = Param.Unsigned(16384,
464 "Associativity of the pattern sequence table")
465 pattern_sequence_table_indexing_policy = Param.BaseIndexingPolicy(
466 SetAssociative(entry_size = 1,
467 assoc = Parent.pattern_sequence_table_assoc,
468 size = Parent.pattern_sequence_table_entries),
469 "Indexing policy of the pattern sequence table")
470 pattern_sequence_table_replacement_policy = Param.BaseReplacementPolicy(
471 LRURP(), "Replacement policy of the pattern sequence table")
472
473 region_miss_order_buffer_entries = Param.Unsigned(131072,
474 "Number of entries of the Region Miss Order Buffer")
475 reconstruction_entries = Param.Unsigned(256,
476 "Number of reconstruction entries")
477
478 class HWPProbeEventRetiredInsts(HWPProbeEvent):
479 def register(self):
480 if self.obj:
481 for name in self.names:
482 self.prefetcher.getCCObject().addEventProbeRetiredInsts(
483 self.obj.getCCObject(), name)
484
485 class PIFPrefetcher(QueuedPrefetcher):
486 type = 'PIFPrefetcher'
487 cxx_class = 'PIFPrefetcher'
488 cxx_header = "mem/cache/prefetch/pif.hh"
489 cxx_exports = [
490 PyBindMethod("addEventProbeRetiredInsts"),
491 ]
492
493 prec_spatial_region_bits = Param.Unsigned(2,
494 "Number of preceding addresses in the spatial region")
495 succ_spatial_region_bits = Param.Unsigned(8,
496 "Number of subsequent addresses in the spatial region")
497 compactor_entries = Param.Unsigned(2, "Entries in the temp. compactor")
498 stream_address_buffer_entries = Param.Unsigned(7, "Entries in the SAB")
499 history_buffer_size = Param.Unsigned(16, "Entries in the history buffer")
500
501 index_entries = Param.MemorySize("64",
502 "Number of entries in the index")
503 index_assoc = Param.Unsigned(64,
504 "Associativity of the index")
505 index_indexing_policy = Param.BaseIndexingPolicy(
506 SetAssociative(entry_size = 1, assoc = Parent.index_assoc,
507 size = Parent.index_entries),
508 "Indexing policy of the index")
509 index_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
510 "Replacement policy of the index")
511
512 def listenFromProbeRetiredInstructions(self, simObj):
513 if not isinstance(simObj, SimObject):
514 raise TypeError("argument must be of SimObject type")
515 self.addEvent(HWPProbeEventRetiredInsts(self, simObj,"RetiredInstsPC"))