src/mem/cache/prefetch/Prefetcher.py

   1 # Copyright (c) 2012, 2014 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
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  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2005 The Regents of The University of Michigan
  14 # All rights reserved.
  15 #
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  17 # modification, are permitted provided that the following conditions are
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  19 # notice, this list of conditions and the following disclaimer;
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  23 # neither the name of the copyright holders nor the names of its
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  25 # this software without specific prior written permission.
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  27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38 #
  39 # Authors: Ron Dreslinski
  40 #          Mitch Hayenga
  41
  42 from ClockedObject import ClockedObject
  43 from m5.SimObject import *
  44 from m5.params import *
  45 from m5.proxy import *
  46 from ReplacementPolicies import *
  47
  48 class HWPProbeEvent(object):
  49     def __init__(self, prefetcher, obj, *listOfNames):
  50         self.obj = obj
  51         self.prefetcher = prefetcher
  52         self.names = listOfNames
  53
  54     def register(self):
  55         if self.obj:
  56             for name in self.names:
  57                 self.prefetcher.getCCObject().addEventProbe(
  58                     self.obj.getCCObject(), name)
  59
  60 class BasePrefetcher(ClockedObject):
  61     type = 'BasePrefetcher'
  62     abstract = True
  63     cxx_header = "mem/cache/prefetch/base.hh"
  64     cxx_exports = [
  65         PyBindMethod("addEventProbe"),
  66     ]
  67     sys = Param.System(Parent.any, "System this prefetcher belongs to")
  68
  69     # Get the block size from the parent (system)
  70     block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
  71
  72     on_miss = Param.Bool(False, "Only notify prefetcher on misses")
  73     on_read = Param.Bool(True, "Notify prefetcher on reads")
  74     on_write = Param.Bool(True, "Notify prefetcher on writes")
  75     on_data  = Param.Bool(True, "Notify prefetcher on data accesses")
  76     on_inst  = Param.Bool(True, "Notify prefetcher on instruction accesses")
  77     prefetch_on_access = Param.Bool(Parent.prefetch_on_access,
  78         "Notify the hardware prefetcher on every access (not just misses)")
  79
  80     _events = []
  81     def addEvent(self, newObject):
  82         self._events.append(newObject)
  83
  84     # Override the normal SimObject::regProbeListeners method and
  85     # register deferred event handlers.
  86     def regProbeListeners(self):
  87         for event in self._events:
  88            event.register()
  89         self.getCCObject().regProbeListeners()
  90
  91     def listenFromProbe(self, simObj, *probeNames):
  92         if not isinstance(simObj, SimObject):
  93             raise TypeError("argument must be of SimObject type")
  94         if len(probeNames) <= 0:
  95             raise TypeError("probeNames must have at least one element")
  96         self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
  97
  98 class QueuedPrefetcher(BasePrefetcher):
  99     type = "QueuedPrefetcher"
 100     abstract = True
 101     cxx_class = "QueuedPrefetcher"
 102     cxx_header = "mem/cache/prefetch/queued.hh"
 103     latency = Param.Int(1, "Latency for generated prefetches")
 104     queue_size = Param.Int(32, "Maximum number of queued prefetches")
 105     queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
 106     queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
 107     cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
 108
 109     tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
 110
 111 class StridePrefetcher(QueuedPrefetcher):
 112     type = 'StridePrefetcher'
 113     cxx_class = 'StridePrefetcher'
 114     cxx_header = "mem/cache/prefetch/stride.hh"
 115
 116     # Do not consult stride prefetcher on instruction accesses
 117     on_inst = False
 118
 119     max_conf = Param.Int(7, "Maximum confidence level")
 120     thresh_conf = Param.Int(4, "Threshold confidence level")
 121     min_conf = Param.Int(0, "Minimum confidence level")
 122     start_conf = Param.Int(4, "Starting confidence for new entries")
 123
 124     table_sets = Param.Int(16, "Number of sets in PC lookup table")
 125     table_assoc = Param.Int(4, "Associativity of PC lookup table")
 126     use_master_id = Param.Bool(True, "Use master id based history")
 127
 128     degree = Param.Int(4, "Number of prefetches to generate")
 129
 130     # Get replacement policy
 131     replacement_policy = Param.BaseReplacementPolicy(RandomRP(),
 132         "Replacement policy")
 133
 134 class TaggedPrefetcher(QueuedPrefetcher):
 135     type = 'TaggedPrefetcher'
 136     cxx_class = 'TaggedPrefetcher'
 137     cxx_header = "mem/cache/prefetch/tagged.hh"
 138
 139     degree = Param.Int(2, "Number of prefetches to generate")