src/mem/cache/prefetch/base.cc

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Mitch Hayenga
  42  */
  43
  44 /**
  45  * @file
  46  * Hardware Prefetcher Definition.
  47  */
  48
  49 #include <list>
  50
  51 #include "base/intmath.hh"
  52 #include "mem/cache/prefetch/base.hh"
  53 #include "mem/cache/base.hh"
  54 #include "sim/system.hh"
  55
  56 BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
  57     : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
  58       system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
  59       onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
  60       masterId(system->getMasterId(name())),
  61       pageBytes(system->getPageBytes())
  62 {
  63 }
  64
  65 void
  66 BasePrefetcher::setCache(BaseCache *_cache)
  67 {
  68     assert(!cache);
  69     cache = _cache;
  70     blkSize = cache->getBlockSize();
  71     lBlkSize = floorLog2(blkSize);
  72 }
  73
  74 void
  75 BasePrefetcher::regStats()
  76 {
  77     pfIssued
  78         .name(name() + ".num_hwpf_issued")
  79         .desc("number of hwpf issued")
  80         ;
  81
  82 }
  83
  84 bool
  85 BasePrefetcher::observeAccess(const PacketPtr &pkt) const
  86 {
  87     Addr addr = pkt->getAddr();
  88     bool fetch = pkt->req->isInstFetch();
  89     bool read = pkt->isRead();
  90     bool inv = pkt->isInvalidate();
  91     bool is_secure = pkt->isSecure();
  92
  93     if (pkt->req->isUncacheable()) return false;
  94     if (fetch && !onInst) return false;
  95     if (!fetch && !onData) return false;
  96     if (!fetch && read && !onRead) return false;
  97     if (!fetch && !read && !onWrite) return false;
  98     if (!fetch && !read && inv) return false;
  99     if (pkt->cmd == MemCmd::CleanEvict) return false;
 100
 101     if (onMiss) {
 102         return !inCache(addr, is_secure) &&
 103                !inMissQueue(addr, is_secure);
 104     }
 105
 106     return true;
 107 }
 108
 109 bool
 110 BasePrefetcher::inCache(Addr addr, bool is_secure) const
 111 {
 112     if (cache->inCache(addr, is_secure)) {
 113         return true;
 114     }
 115     return false;
 116 }
 117
 118 bool
 119 BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
 120 {
 121     if (cache->inMissQueue(addr, is_secure)) {
 122         return true;
 123     }
 124     return false;
 125 }
 126
 127 bool
 128 BasePrefetcher::samePage(Addr a, Addr b) const
 129 {
 130     return roundDown(a, pageBytes) == roundDown(b, pageBytes);
 131 }
 132
 133 Addr
 134 BasePrefetcher::blockAddress(Addr a) const
 135 {
 136     return a & ~(blkSize-1);
 137 }
 138
 139 Addr
 140 BasePrefetcher::blockIndex(Addr a) const
 141 {
 142     return a >> lBlkSize;
 143 }
 144
 145 Addr
 146 BasePrefetcher::pageAddress(Addr a) const
 147 {
 148     return roundDown(a, pageBytes);
 149 }
 150
 151 Addr
 152 BasePrefetcher::pageOffset(Addr a) const
 153 {
 154     return a & (pageBytes - 1);
 155 }
 156
 157 Addr
 158 BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
 159 {
 160     return page + (blockIndex << lBlkSize);
 161 }