src/mem/cache/prefetch/base.cc

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Mitch Hayenga
  42  */
  43
  44 /**
  45  * @file
  46  * Hardware Prefetcher Definition.
  47  */
  48
  49 #include "mem/cache/prefetch/base.hh"
  50
  51 #include <cassert>
  52
  53 #include "base/intmath.hh"
  54 #include "mem/cache/base.hh"
  55 #include "params/BasePrefetcher.hh"
  56 #include "sim/system.hh"
  57
  58 BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
  59     : ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
  60       system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
  61       onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
  62       masterId(system->getMasterId(this)),
  63       pageBytes(system->getPageBytes())
  64 {
  65 }
  66
  67 void
  68 BasePrefetcher::setCache(BaseCache *_cache)
  69 {
  70     assert(!cache);
  71     cache = _cache;
  72     blkSize = cache->getBlockSize();
  73     lBlkSize = floorLog2(blkSize);
  74 }
  75
  76 void
  77 BasePrefetcher::regStats()
  78 {
  79     ClockedObject::regStats();
  80
  81     pfIssued
  82         .name(name() + ".num_hwpf_issued")
  83         .desc("number of hwpf issued")
  84         ;
  85
  86 }
  87
  88 bool
  89 BasePrefetcher::observeAccess(const PacketPtr &pkt) const
  90 {
  91     Addr addr = pkt->getAddr();
  92     bool fetch = pkt->req->isInstFetch();
  93     bool read = pkt->isRead();
  94     bool inv = pkt->isInvalidate();
  95     bool is_secure = pkt->isSecure();
  96
  97     if (pkt->req->isUncacheable()) return false;
  98     if (fetch && !onInst) return false;
  99     if (!fetch && !onData) return false;
 100     if (!fetch && read && !onRead) return false;
 101     if (!fetch && !read && !onWrite) return false;
 102     if (!fetch && !read && inv) return false;
 103     if (pkt->cmd == MemCmd::CleanEvict) return false;
 104
 105     if (onMiss) {
 106         return !inCache(addr, is_secure) &&
 107                !inMissQueue(addr, is_secure);
 108     }
 109
 110     return true;
 111 }
 112
 113 bool
 114 BasePrefetcher::inCache(Addr addr, bool is_secure) const
 115 {
 116     if (cache->inCache(addr, is_secure)) {
 117         return true;
 118     }
 119     return false;
 120 }
 121
 122 bool
 123 BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
 124 {
 125     if (cache->inMissQueue(addr, is_secure)) {
 126         return true;
 127     }
 128     return false;
 129 }
 130
 131 bool
 132 BasePrefetcher::samePage(Addr a, Addr b) const
 133 {
 134     return roundDown(a, pageBytes) == roundDown(b, pageBytes);
 135 }
 136
 137 Addr
 138 BasePrefetcher::blockAddress(Addr a) const
 139 {
 140     return a & ~(blkSize-1);
 141 }
 142
 143 Addr
 144 BasePrefetcher::blockIndex(Addr a) const
 145 {
 146     return a >> lBlkSize;
 147 }
 148
 149 Addr
 150 BasePrefetcher::pageAddress(Addr a) const
 151 {
 152     return roundDown(a, pageBytes);
 153 }
 154
 155 Addr
 156 BasePrefetcher::pageOffset(Addr a) const
 157 {
 158     return a & (pageBytes - 1);
 159 }
 160
 161 Addr
 162 BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
 163 {
 164     return page + (blockIndex << lBlkSize);
 165 }