2 * Copyright (c) 2013-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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8 * to a hardware implementation of the functionality of the software
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
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22 * notice, this list of conditions and the following disclaimer in the
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Ron Dreslinski
46 * Hardware Prefetcher Definition.
49 #include "mem/cache/prefetch/base.hh"
53 #include "base/intmath.hh"
54 #include "mem/cache/base.hh"
55 #include "params/BasePrefetcher.hh"
56 #include "sim/system.hh"
58 BasePrefetcher::BasePrefetcher(const BasePrefetcherParams
*p
)
59 : ClockedObject(p
), cache(nullptr), blkSize(0), lBlkSize(0),
60 system(p
->sys
), onMiss(p
->on_miss
), onRead(p
->on_read
),
61 onWrite(p
->on_write
), onData(p
->on_data
), onInst(p
->on_inst
),
62 masterId(system
->getMasterId(this)),
63 pageBytes(system
->getPageBytes())
68 BasePrefetcher::setCache(BaseCache
*_cache
)
72 blkSize
= cache
->getBlockSize();
73 lBlkSize
= floorLog2(blkSize
);
77 BasePrefetcher::regStats()
79 ClockedObject::regStats();
82 .name(name() + ".num_hwpf_issued")
83 .desc("number of hwpf issued")
89 BasePrefetcher::observeAccess(const PacketPtr
&pkt
) const
91 Addr addr
= pkt
->getAddr();
92 bool fetch
= pkt
->req
->isInstFetch();
93 bool read
= pkt
->isRead();
94 bool inv
= pkt
->isInvalidate();
95 bool is_secure
= pkt
->isSecure();
97 if (pkt
->req
->isUncacheable()) return false;
98 if (fetch
&& !onInst
) return false;
99 if (!fetch
&& !onData
) return false;
100 if (!fetch
&& read
&& !onRead
) return false;
101 if (!fetch
&& !read
&& !onWrite
) return false;
102 if (!fetch
&& !read
&& inv
) return false;
103 if (pkt
->cmd
== MemCmd::CleanEvict
) return false;
106 return !inCache(addr
, is_secure
) &&
107 !inMissQueue(addr
, is_secure
);
114 BasePrefetcher::inCache(Addr addr
, bool is_secure
) const
116 if (cache
->inCache(addr
, is_secure
)) {
123 BasePrefetcher::inMissQueue(Addr addr
, bool is_secure
) const
125 if (cache
->inMissQueue(addr
, is_secure
)) {
132 BasePrefetcher::samePage(Addr a
, Addr b
) const
134 return roundDown(a
, pageBytes
) == roundDown(b
, pageBytes
);
138 BasePrefetcher::blockAddress(Addr a
) const
140 return a
& ~(blkSize
-1);
144 BasePrefetcher::blockIndex(Addr a
) const
146 return a
>> lBlkSize
;
150 BasePrefetcher::pageAddress(Addr a
) const
152 return roundDown(a
, pageBytes
);
156 BasePrefetcher::pageOffset(Addr a
) const
158 return a
& (pageBytes
- 1);
162 BasePrefetcher::pageIthBlockAddress(Addr page
, uint32_t blockIndex
) const
164 return page
+ (blockIndex
<< lBlkSize
);