57c1424bf7e466ef72fb55755a8512d10e1137a1
2 * Copyright (c) 2013 ARM Limited
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14 * Copyright (c) 2005 The Regents of The University of Michigan
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40 * Authors: Ron Dreslinski
45 * Hardware Prefetcher Definition.
50 #include "arch/isa_traits.hh"
51 #include "base/trace.hh"
52 #include "config/the_isa.hh"
53 #include "debug/HWPrefetch.hh"
54 #include "mem/cache/prefetch/base.hh"
55 #include "mem/cache/base.hh"
56 #include "mem/request.hh"
57 #include "sim/system.hh"
59 BasePrefetcher::BasePrefetcher(const Params
*p
)
60 : ClockedObject(p
), size(p
->size
), latency(p
->latency
), degree(p
->degree
),
61 useMasterId(p
->use_master_id
), pageStop(!p
->cross_pages
),
62 serialSquash(p
->serial_squash
), onlyData(p
->data_accesses_only
),
63 onMissOnly(p
->on_miss_only
), onReadOnly(p
->on_read_only
),
64 onPrefetch(p
->on_prefetch
), system(p
->sys
),
65 masterId(system
->getMasterId(name()))
70 BasePrefetcher::setCache(BaseCache
*_cache
)
73 blkSize
= cache
->getBlockSize();
77 BasePrefetcher::regStats()
80 .name(name() + ".prefetcher.num_hwpf_identified")
81 .desc("number of hwpf identified")
85 .name(name() + ".prefetcher.num_hwpf_already_in_mshr")
86 .desc("number of hwpf that were already in mshr")
90 .name(name() + ".prefetcher.num_hwpf_already_in_cache")
91 .desc("number of hwpf that were already in the cache")
95 .name(name() + ".prefetcher.num_hwpf_already_in_prefetcher")
96 .desc("number of hwpf that were already in the prefetch queue")
100 .name(name() + ".prefetcher.num_hwpf_evicted")
101 .desc("number of hwpf removed due to no buffer left")
105 .name(name() + ".prefetcher.num_hwpf_removed_MSHR_hit")
106 .desc("number of hwpf removed because MSHR allocated")
110 .name(name() + ".prefetcher.num_hwpf_issued")
111 .desc("number of hwpf issued")
115 .name(name() + ".prefetcher.num_hwpf_span_page")
116 .desc("number of hwpf spanning a virtual page")
120 .name(name() + ".prefetcher.num_hwpf_squashed_from_miss")
121 .desc("number of hwpf that got squashed due to a miss "
122 "aborting calculation time")
127 BasePrefetcher::inCache(Addr addr
, bool is_secure
)
129 if (cache
->inCache(addr
, is_secure
)) {
137 BasePrefetcher::inMissQueue(Addr addr
, bool is_secure
)
139 if (cache
->inMissQueue(addr
, is_secure
)) {
147 BasePrefetcher::getPacket()
149 DPRINTF(HWPrefetch
, "Requesting a hw_pf to issue\n");
152 DPRINTF(HWPrefetch
, "No HW_PF found\n");
156 PacketPtr pkt
= pf
.begin()->pkt
;
157 while (!pf
.empty()) {
158 pkt
= pf
.begin()->pkt
;
161 Addr blk_addr
= pkt
->getAddr() & ~(Addr
)(blkSize
-1);
162 bool is_secure
= pkt
->isSecure();
164 if (!inCache(blk_addr
, is_secure
) && !inMissQueue(blk_addr
, is_secure
))
165 // we found a prefetch, return it
168 DPRINTF(HWPrefetch
, "addr 0x%x (%s) in cache, skipping\n",
169 pkt
->getAddr(), is_secure
? "s" : "ns");
174 cache
->deassertMemSideBusRequest(BaseCache::Request_PF
);
175 return NULL
; // None left, all were in cache
181 DPRINTF(HWPrefetch
, "returning 0x%x (%s)\n", pkt
->getAddr(),
182 pkt
->isSecure() ? "s" : "ns");
188 BasePrefetcher::notify(PacketPtr
&pkt
, Tick tick
)
190 // Don't consult the prefetcher if any of the following conditons are true
191 // 1) The request is uncacheable
192 // 2) The request is a fetch, but we are only prefeching data
193 // 3) The request is a cache hit, but we are only training on misses
194 // 4) THe request is a write, but we are only training on reads
195 if (!pkt
->req
->isUncacheable() && !(pkt
->req
->isInstFetch() && onlyData
) &&
196 !(onMissOnly
&& inCache(pkt
->getAddr(), true)) &&
197 !(onReadOnly
&& !pkt
->isRead())) {
198 // Calculate the blk address
199 Addr blk_addr
= pkt
->getAddr() & ~(Addr
)(blkSize
-1);
200 bool is_secure
= pkt
->isSecure();
202 // Check if miss is in pfq, if so remove it
203 std::list
<DeferredPacket
>::iterator iter
= inPrefetch(blk_addr
,
205 if (iter
!= pf
.end()) {
206 DPRINTF(HWPrefetch
, "Saw a miss to a queued prefetch addr: "
207 "0x%x (%s), removing it\n", blk_addr
,
208 is_secure
? "s" : "ns");
210 delete iter
->pkt
->req
;
212 iter
= pf
.erase(iter
);
214 cache
->deassertMemSideBusRequest(BaseCache::Request_PF
);
217 // Remove anything in queue with delay older than time
218 // since everything is inserted in time order, start from end
219 // and work until pf.empty() or time is earlier
220 // This is done to emulate Aborting the previous work on a new miss
221 // Needed for serial calculators like GHB
224 if (iter
!= pf
.begin())
226 while (!pf
.empty() && iter
->tick
>= tick
) {
228 DPRINTF(HWPrefetch
, "Squashing old prefetch addr: 0x%x\n",
229 iter
->pkt
->getAddr());
230 delete iter
->pkt
->req
;
232 iter
= pf
.erase(iter
);
233 if (iter
!= pf
.begin())
237 cache
->deassertMemSideBusRequest(BaseCache::Request_PF
);
241 std::list
<Addr
> addresses
;
242 std::list
<Cycles
> delays
;
243 calculatePrefetch(pkt
, addresses
, delays
);
245 std::list
<Addr
>::iterator addrIter
= addresses
.begin();
246 std::list
<Cycles
>::iterator delayIter
= delays
.begin();
247 for (; addrIter
!= addresses
.end(); ++addrIter
, ++delayIter
) {
248 Addr addr
= *addrIter
;
252 DPRINTF(HWPrefetch
, "Found a pf candidate addr: 0x%x, "
253 "inserting into prefetch queue with delay %d time %d\n",
254 addr
, *delayIter
, time
);
256 // Check if it is already in the pf buffer
257 if (inPrefetch(addr
, is_secure
) != pf
.end()) {
259 DPRINTF(HWPrefetch
, "Prefetch addr already in pf buffer\n");
263 // create a prefetch memreq
264 Request
*prefetchReq
= new Request(*addrIter
, blkSize
, 0, masterId
);
266 prefetchReq
->setFlags(Request::SECURE
);
267 prefetchReq
->taskId(ContextSwitchTaskId::Prefetcher
);
269 new Packet(prefetchReq
, MemCmd::HardPFReq
);
270 prefetch
->allocate();
271 prefetch
->req
->setThreadContext(pkt
->req
->contextId(),
272 pkt
->req
->threadId());
274 // Tag orefetch reqeuests with corresponding PC to train lower
275 // cache-level prefetchers
276 if (onPrefetch
&& pkt
->req
->hasPC())
277 prefetch
->req
->setPC(pkt
->req
->getPC());
279 // We just remove the head if we are full
280 if (pf
.size() == size
) {
282 PacketPtr old_pkt
= pf
.begin()->pkt
;
283 DPRINTF(HWPrefetch
, "Prefetch queue full, "
284 "removing oldest 0x%x\n", old_pkt
->getAddr());
290 pf
.push_back(DeferredPacket(tick
+ clockPeriod() * *delayIter
,
295 return pf
.empty() ? 0 : pf
.front().tick
;
298 std::list
<BasePrefetcher::DeferredPacket
>::iterator
299 BasePrefetcher::inPrefetch(Addr address
, bool is_secure
)
301 // Guaranteed to only be one match, we always check before inserting
302 std::list
<DeferredPacket
>::iterator iter
;
303 for (iter
= pf
.begin(); iter
!= pf
.end(); iter
++) {
304 if (((*iter
).pkt
->getAddr() & ~(Addr
)(blkSize
-1)) == address
&&
305 (*iter
).pkt
->isSecure() == is_secure
) {
313 BasePrefetcher::samePage(Addr a
, Addr b
)
315 return roundDown(a
, TheISA::PageBytes
) == roundDown(b
, TheISA::PageBytes
);