src/mem/cache/prefetch/base.cc

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Mitch Hayenga
  42  */
  43
  44 /**
  45  * @file
  46  * Hardware Prefetcher Definition.
  47  */
  48
  49 #include "mem/cache/prefetch/base.hh"
  50
  51 #include <cassert>
  52
  53 #include "base/intmath.hh"
  54 #include "cpu/base.hh"
  55 #include "mem/cache/base.hh"
  56 #include "params/BasePrefetcher.hh"
  57 #include "sim/system.hh"
  58
  59 BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
  60   : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
  61     masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
  62     secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
  63     paddress(pkt->req->getPaddr()), cacheMiss(miss)
  64 {
  65     unsigned int req_size = pkt->req->getSize();
  66     if (!write && miss) {
  67         data = nullptr;
  68     } else {
  69         data = new uint8_t[req_size];
  70         Addr offset = pkt->req->getPaddr() - pkt->getAddr();
  71         std::memcpy(data, &(pkt->getConstPtr<uint8_t>()[offset]), req_size);
  72     }
  73 }
  74
  75 BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr addr)
  76   : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC),
  77     secure(pfi.secure), size(pfi.size), write(pfi.write),
  78     paddress(pfi.paddress), cacheMiss(pfi.cacheMiss), data(nullptr)
  79 {
  80 }
  81
  82 void
  83 BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
  84 {
  85     if (isFill) {
  86         parent.notifyFill(pkt);
  87     } else {
  88         parent.probeNotify(pkt, miss);
  89     }
  90 }
  91
  92 BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
  93     : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
  94       lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
  95       onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
  96       masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
  97       prefetchOnAccess(p->prefetch_on_access),
  98       useVirtualAddresses(p->use_virtual_addresses), issuedPrefetches(0),
  99       usefulPrefetches(0), tlb(nullptr)
 100 {
 101 }
 102
 103 void
 104 BasePrefetcher::setCache(BaseCache *_cache)
 105 {
 106     assert(!cache);
 107     cache = _cache;
 108
 109     // If the cache has a different block size from the system's, save it
 110     blkSize = cache->getBlockSize();
 111     lBlkSize = floorLog2(blkSize);
 112 }
 113
 114 void
 115 BasePrefetcher::regStats()
 116 {
 117     ClockedObject::regStats();
 118
 119     pfIssued
 120         .name(name() + ".num_hwpf_issued")
 121         .desc("number of hwpf issued")
 122         ;
 123
 124 }
 125
 126 bool
 127 BasePrefetcher::observeAccess(const PacketPtr &pkt, bool miss) const
 128 {
 129     bool fetch = pkt->req->isInstFetch();
 130     bool read = pkt->isRead();
 131     bool inv = pkt->isInvalidate();
 132
 133     if (pkt->req->isUncacheable()) return false;
 134     if (fetch && !onInst) return false;
 135     if (!fetch && !onData) return false;
 136     if (!fetch && read && !onRead) return false;
 137     if (!fetch && !read && !onWrite) return false;
 138     if (!fetch && !read && inv) return false;
 139     if (pkt->cmd == MemCmd::CleanEvict) return false;
 140
 141     if (onMiss) {
 142         return miss;
 143     }
 144
 145     return true;
 146 }
 147
 148 bool
 149 BasePrefetcher::inCache(Addr addr, bool is_secure) const
 150 {
 151     return cache->inCache(addr, is_secure);
 152 }
 153
 154 bool
 155 BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
 156 {
 157     return cache->inMissQueue(addr, is_secure);
 158 }
 159
 160 bool
 161 BasePrefetcher::hasBeenPrefetched(Addr addr, bool is_secure) const
 162 {
 163     return cache->hasBeenPrefetched(addr, is_secure);
 164 }
 165
 166 bool
 167 BasePrefetcher::samePage(Addr a, Addr b) const
 168 {
 169     return roundDown(a, pageBytes) == roundDown(b, pageBytes);
 170 }
 171
 172 Addr
 173 BasePrefetcher::blockAddress(Addr a) const
 174 {
 175     return a & ~((Addr)blkSize-1);
 176 }
 177
 178 Addr
 179 BasePrefetcher::blockIndex(Addr a) const
 180 {
 181     return a >> lBlkSize;
 182 }
 183
 184 Addr
 185 BasePrefetcher::pageAddress(Addr a) const
 186 {
 187     return roundDown(a, pageBytes);
 188 }
 189
 190 Addr
 191 BasePrefetcher::pageOffset(Addr a) const
 192 {
 193     return a & (pageBytes - 1);
 194 }
 195
 196 Addr
 197 BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
 198 {
 199     return page + (blockIndex << lBlkSize);
 200 }
 201
 202 void
 203 BasePrefetcher::probeNotify(const PacketPtr &pkt, bool miss)
 204 {
 205     // Don't notify prefetcher on SWPrefetch, cache maintenance
 206     // operations or for writes that we are coaslescing.
 207     if (pkt->cmd.isSWPrefetch()) return;
 208     if (pkt->req->isCacheMaintenance()) return;
 209     if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
 210     if (!pkt->req->hasPaddr()) {
 211         panic("Request must have a physical address");
 212     }
 213
 214     if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
 215         usefulPrefetches += 1;
 216     }
 217
 218     // Verify this access type is observed by prefetcher
 219     if (observeAccess(pkt, miss)) {
 220         if (useVirtualAddresses && pkt->req->hasVaddr()) {
 221             PrefetchInfo pfi(pkt, pkt->req->getVaddr(), miss);
 222             notify(pkt, pfi);
 223         } else if (!useVirtualAddresses) {
 224             PrefetchInfo pfi(pkt, pkt->req->getPaddr(), miss);
 225             notify(pkt, pfi);
 226         }
 227     }
 228 }
 229
 230 void
 231 BasePrefetcher::regProbeListeners()
 232 {
 233     /**
 234      * If no probes were added by the configuration scripts, connect to the
 235      * parent cache using the probe "Miss". Also connect to "Hit", if the
 236      * cache is configured to prefetch on accesses.
 237      */
 238     if (listeners.empty() && cache != nullptr) {
 239         ProbeManager *pm(cache->getProbeManager());
 240         listeners.push_back(new PrefetchListener(*this, pm, "Miss", false,
 241                                                 true));
 242         listeners.push_back(new PrefetchListener(*this, pm, "Fill", true,
 243                                                  false));
 244         if (prefetchOnAccess) {
 245             listeners.push_back(new PrefetchListener(*this, pm, "Hit", false,
 246                                                      false));
 247         }
 248     }
 249 }
 250
 251 void
 252 BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
 253 {
 254     ProbeManager *pm(obj->getProbeManager());
 255     listeners.push_back(new PrefetchListener(*this, pm, name));
 256 }
 257
 258 void
 259 BasePrefetcher::addTLB(BaseTLB *t)
 260 {
 261     fatal_if(tlb != nullptr, "Only one TLB can be registered");
 262     tlb = t;
 263 }