src/mem/cache/prefetch/base.cc

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /**
  42  * @file
  43  * Hardware Prefetcher Definition.
  44  */
  45
  46 #include "mem/cache/prefetch/base.hh"
  47
  48 #include <cassert>
  49
  50 #include "base/intmath.hh"
  51 #include "mem/cache/base.hh"
  52 #include "params/BasePrefetcher.hh"
  53 #include "sim/system.hh"
  54
  55 namespace Prefetcher {
  56
  57 Base::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
  58   : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
  59     requestorId(pkt->req->requestorId()), validPC(pkt->req->hasPC()),
  60     secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()),
  61     paddress(pkt->req->getPaddr()), cacheMiss(miss)
  62 {
  63     unsigned int req_size = pkt->req->getSize();
  64     if (!write && miss) {
  65         data = nullptr;
  66     } else {
  67         data = new uint8_t[req_size];
  68         Addr offset = pkt->req->getPaddr() - pkt->getAddr();
  69         std::memcpy(data, &(pkt->getConstPtr<uint8_t>()[offset]), req_size);
  70     }
  71 }
  72
  73 Base::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr addr)
  74   : address(addr), pc(pfi.pc), requestorId(pfi.requestorId),
  75     validPC(pfi.validPC), secure(pfi.secure), size(pfi.size),
  76     write(pfi.write), paddress(pfi.paddress), cacheMiss(pfi.cacheMiss),
  77     data(nullptr)
  78 {
  79 }
  80
  81 void
  82 Base::PrefetchListener::notify(const PacketPtr &pkt)
  83 {
  84     if (isFill) {
  85         parent.notifyFill(pkt);
  86     } else {
  87         parent.probeNotify(pkt, miss);
  88     }
  89 }
  90
  91 Base::Base(const BasePrefetcherParams &p)
  92     : ClockedObject(p), listeners(), cache(nullptr), blkSize(p.block_size),
  93       lBlkSize(floorLog2(blkSize)), onMiss(p.on_miss), onRead(p.on_read),
  94       onWrite(p.on_write), onData(p.on_data), onInst(p.on_inst),
  95       requestorId(p.sys->getRequestorId(this)),
  96       pageBytes(p.sys->getPageBytes()),
  97       prefetchOnAccess(p.prefetch_on_access),
  98       useVirtualAddresses(p.use_virtual_addresses),
  99       prefetchStats(this), issuedPrefetches(0),
 100       usefulPrefetches(0), tlb(nullptr)
 101 {
 102 }
 103
 104 void
 105 Base::setCache(BaseCache *_cache)
 106 {
 107     assert(!cache);
 108     cache = _cache;
 109
 110     // If the cache has a different block size from the system's, save it
 111     blkSize = cache->getBlockSize();
 112     lBlkSize = floorLog2(blkSize);
 113 }
 114 Base::StatGroup::StatGroup(Stats::Group *parent)
 115     : Stats::Group(parent),
 116     ADD_STAT(pfIssued, "number of hwpf issued")
 117 {
 118 }
 119
 120
 121 bool
 122 Base::observeAccess(const PacketPtr &pkt, bool miss) const
 123 {
 124     bool fetch = pkt->req->isInstFetch();
 125     bool read = pkt->isRead();
 126     bool inv = pkt->isInvalidate();
 127
 128     if (!miss && !prefetchOnAccess) return false;
 129     if (pkt->req->isUncacheable()) return false;
 130     if (fetch && !onInst) return false;
 131     if (!fetch && !onData) return false;
 132     if (!fetch && read && !onRead) return false;
 133     if (!fetch && !read && !onWrite) return false;
 134     if (!fetch && !read && inv) return false;
 135     if (pkt->cmd == MemCmd::CleanEvict) return false;
 136
 137     if (onMiss) {
 138         return miss;
 139     }
 140
 141     return true;
 142 }
 143
 144 bool
 145 Base::inCache(Addr addr, bool is_secure) const
 146 {
 147     return cache->inCache(addr, is_secure);
 148 }
 149
 150 bool
 151 Base::inMissQueue(Addr addr, bool is_secure) const
 152 {
 153     return cache->inMissQueue(addr, is_secure);
 154 }
 155
 156 bool
 157 Base::hasBeenPrefetched(Addr addr, bool is_secure) const
 158 {
 159     return cache->hasBeenPrefetched(addr, is_secure);
 160 }
 161
 162 bool
 163 Base::samePage(Addr a, Addr b) const
 164 {
 165     return roundDown(a, pageBytes) == roundDown(b, pageBytes);
 166 }
 167
 168 Addr
 169 Base::blockAddress(Addr a) const
 170 {
 171     return a & ~((Addr)blkSize-1);
 172 }
 173
 174 Addr
 175 Base::blockIndex(Addr a) const
 176 {
 177     return a >> lBlkSize;
 178 }
 179
 180 Addr
 181 Base::pageAddress(Addr a) const
 182 {
 183     return roundDown(a, pageBytes);
 184 }
 185
 186 Addr
 187 Base::pageOffset(Addr a) const
 188 {
 189     return a & (pageBytes - 1);
 190 }
 191
 192 Addr
 193 Base::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
 194 {
 195     return page + (blockIndex << lBlkSize);
 196 }
 197
 198 void
 199 Base::probeNotify(const PacketPtr &pkt, bool miss)
 200 {
 201     // Don't notify prefetcher on SWPrefetch, cache maintenance
 202     // operations or for writes that we are coaslescing.
 203     if (pkt->cmd.isSWPrefetch()) return;
 204     if (pkt->req->isCacheMaintenance()) return;
 205     if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
 206     if (!pkt->req->hasPaddr()) {
 207         panic("Request must have a physical address");
 208     }
 209
 210     if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
 211         usefulPrefetches += 1;
 212     }
 213
 214     // Verify this access type is observed by prefetcher
 215     if (observeAccess(pkt, miss)) {
 216         if (useVirtualAddresses && pkt->req->hasVaddr()) {
 217             PrefetchInfo pfi(pkt, pkt->req->getVaddr(), miss);
 218             notify(pkt, pfi);
 219         } else if (!useVirtualAddresses) {
 220             PrefetchInfo pfi(pkt, pkt->req->getPaddr(), miss);
 221             notify(pkt, pfi);
 222         }
 223     }
 224 }
 225
 226 void
 227 Base::regProbeListeners()
 228 {
 229     /**
 230      * If no probes were added by the configuration scripts, connect to the
 231      * parent cache using the probe "Miss". Also connect to "Hit", if the
 232      * cache is configured to prefetch on accesses.
 233      */
 234     if (listeners.empty() && cache != nullptr) {
 235         ProbeManager *pm(cache->getProbeManager());
 236         listeners.push_back(new PrefetchListener(*this, pm, "Miss", false,
 237                                                 true));
 238         listeners.push_back(new PrefetchListener(*this, pm, "Fill", true,
 239                                                  false));
 240         listeners.push_back(new PrefetchListener(*this, pm, "Hit", false,
 241                                                  false));
 242     }
 243 }
 244
 245 void
 246 Base::addEventProbe(SimObject *obj, const char *name)
 247 {
 248     ProbeManager *pm(obj->getProbeManager());
 249     listeners.push_back(new PrefetchListener(*this, pm, name));
 250 }
 251
 252 void
 253 Base::addTLB(BaseTLB *t)
 254 {
 255     fatal_if(tlb != nullptr, "Only one TLB can be registered");
 256     tlb = t;
 257 }
 258
 259 } // namespace Prefetcher