2 * Copyright (c) 2013-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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8 * to a hardware implementation of the functionality of the software
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
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25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Ron Dreslinski
46 * Hardware Prefetcher Definition.
49 #include "mem/cache/prefetch/base.hh"
53 #include "base/intmath.hh"
54 #include "cpu/base.hh"
55 #include "mem/cache/base.hh"
56 #include "params/BasePrefetcher.hh"
57 #include "sim/system.hh"
59 BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt
, Addr addr
)
60 : address(addr
), pc(pkt
->req
->hasPC() ? pkt
->req
->getPC() : 0),
61 masterId(pkt
->req
->masterId()), validPC(pkt
->req
->hasPC()),
62 secure(pkt
->isSecure())
66 BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo
const &pfi
, Addr addr
)
67 : address(addr
), pc(pfi
.pc
), masterId(pfi
.masterId
), validPC(pfi
.validPC
),
73 BasePrefetcher::PrefetchListener::notify(const PacketPtr
&pkt
)
75 parent
.probeNotify(pkt
);
78 BasePrefetcher::BasePrefetcher(const BasePrefetcherParams
*p
)
79 : ClockedObject(p
), listeners(), cache(nullptr), blkSize(p
->block_size
),
80 lBlkSize(floorLog2(blkSize
)), onMiss(p
->on_miss
), onRead(p
->on_read
),
81 onWrite(p
->on_write
), onData(p
->on_data
), onInst(p
->on_inst
),
82 masterId(p
->sys
->getMasterId(this)), pageBytes(p
->sys
->getPageBytes()),
83 prefetchOnAccess(p
->prefetch_on_access
),
84 useVirtualAddresses(p
->use_virtual_addresses
)
89 BasePrefetcher::setCache(BaseCache
*_cache
)
94 // If the cache has a different block size from the system's, save it
95 blkSize
= cache
->getBlockSize();
96 lBlkSize
= floorLog2(blkSize
);
100 BasePrefetcher::regStats()
102 ClockedObject::regStats();
105 .name(name() + ".num_hwpf_issued")
106 .desc("number of hwpf issued")
112 BasePrefetcher::observeAccess(const PacketPtr
&pkt
) const
114 Addr addr
= pkt
->getAddr();
115 bool fetch
= pkt
->req
->isInstFetch();
116 bool read
= pkt
->isRead();
117 bool inv
= pkt
->isInvalidate();
118 bool is_secure
= pkt
->isSecure();
120 if (pkt
->req
->isUncacheable()) return false;
121 if (fetch
&& !onInst
) return false;
122 if (!fetch
&& !onData
) return false;
123 if (!fetch
&& read
&& !onRead
) return false;
124 if (!fetch
&& !read
&& !onWrite
) return false;
125 if (!fetch
&& !read
&& inv
) return false;
126 if (pkt
->cmd
== MemCmd::CleanEvict
) return false;
129 return !inCache(addr
, is_secure
) &&
130 !inMissQueue(addr
, is_secure
);
137 BasePrefetcher::inCache(Addr addr
, bool is_secure
) const
139 return cache
->inCache(addr
, is_secure
);
143 BasePrefetcher::inMissQueue(Addr addr
, bool is_secure
) const
145 return cache
->inMissQueue(addr
, is_secure
);
149 BasePrefetcher::samePage(Addr a
, Addr b
) const
151 return roundDown(a
, pageBytes
) == roundDown(b
, pageBytes
);
155 BasePrefetcher::blockAddress(Addr a
) const
157 return a
& ~((Addr
)blkSize
-1);
161 BasePrefetcher::blockIndex(Addr a
) const
163 return a
>> lBlkSize
;
167 BasePrefetcher::pageAddress(Addr a
) const
169 return roundDown(a
, pageBytes
);
173 BasePrefetcher::pageOffset(Addr a
) const
175 return a
& (pageBytes
- 1);
179 BasePrefetcher::pageIthBlockAddress(Addr page
, uint32_t blockIndex
) const
181 return page
+ (blockIndex
<< lBlkSize
);
185 BasePrefetcher::probeNotify(const PacketPtr
&pkt
)
187 // Don't notify prefetcher on SWPrefetch, cache maintenance
188 // operations or for writes that we are coaslescing.
189 if (pkt
->cmd
.isSWPrefetch()) return;
190 if (pkt
->req
->isCacheMaintenance()) return;
191 if (pkt
->isWrite() && cache
!= nullptr && cache
->coalesce()) return;
193 // Verify this access type is observed by prefetcher
194 if (observeAccess(pkt
)) {
195 if (useVirtualAddresses
&& pkt
->req
->hasVaddr()) {
196 PrefetchInfo
pfi(pkt
, pkt
->req
->getVaddr());
198 } else if (!useVirtualAddresses
&& pkt
->req
->hasPaddr()) {
199 PrefetchInfo
pfi(pkt
, pkt
->req
->getPaddr());
206 BasePrefetcher::regProbeListeners()
209 * If no probes were added by the configuration scripts, connect to the
210 * parent cache using the probe "Miss". Also connect to "Hit", if the
211 * cache is configured to prefetch on accesses.
213 if (listeners
.empty() && cache
!= nullptr) {
214 ProbeManager
*pm(cache
->getProbeManager());
215 listeners
.push_back(new PrefetchListener(*this, pm
, "Miss"));
216 if (prefetchOnAccess
) {
217 listeners
.push_back(new PrefetchListener(*this, pm
, "Hit"));
223 BasePrefetcher::addEventProbe(SimObject
*obj
, const char *name
)
225 ProbeManager
*pm(obj
->getProbeManager());
226 listeners
.push_back(new PrefetchListener(*this, pm
, name
));