src/mem/cache/prefetch/base.cc

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Mitch Hayenga
  42  */
  43
  44 /**
  45  * @file
  46  * Hardware Prefetcher Definition.
  47  */
  48
  49 #include "mem/cache/prefetch/base.hh"
  50
  51 #include <cassert>
  52
  53 #include "base/intmath.hh"
  54 #include "cpu/base.hh"
  55 #include "mem/cache/base.hh"
  56 #include "params/BasePrefetcher.hh"
  57 #include "sim/system.hh"
  58
  59 BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr)
  60   : address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
  61     masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
  62     secure(pkt->isSecure())
  63 {
  64 }
  65
  66 BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr addr)
  67   : address(addr), pc(pfi.pc), masterId(pfi.masterId), validPC(pfi.validPC),
  68     secure(pfi.secure)
  69 {
  70 }
  71
  72 void
  73 BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
  74 {
  75     parent.probeNotify(pkt);
  76 }
  77
  78 BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
  79     : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
  80       lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
  81       onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
  82       masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
  83       prefetchOnAccess(p->prefetch_on_access),
  84       useVirtualAddresses(p->use_virtual_addresses)
  85 {
  86 }
  87
  88 void
  89 BasePrefetcher::setCache(BaseCache *_cache)
  90 {
  91     assert(!cache);
  92     cache = _cache;
  93
  94     // If the cache has a different block size from the system's, save it
  95     blkSize = cache->getBlockSize();
  96     lBlkSize = floorLog2(blkSize);
  97 }
  98
  99 void
 100 BasePrefetcher::regStats()
 101 {
 102     ClockedObject::regStats();
 103
 104     pfIssued
 105         .name(name() + ".num_hwpf_issued")
 106         .desc("number of hwpf issued")
 107         ;
 108
 109 }
 110
 111 bool
 112 BasePrefetcher::observeAccess(const PacketPtr &pkt) const
 113 {
 114     Addr addr = pkt->getAddr();
 115     bool fetch = pkt->req->isInstFetch();
 116     bool read = pkt->isRead();
 117     bool inv = pkt->isInvalidate();
 118     bool is_secure = pkt->isSecure();
 119
 120     if (pkt->req->isUncacheable()) return false;
 121     if (fetch && !onInst) return false;
 122     if (!fetch && !onData) return false;
 123     if (!fetch && read && !onRead) return false;
 124     if (!fetch && !read && !onWrite) return false;
 125     if (!fetch && !read && inv) return false;
 126     if (pkt->cmd == MemCmd::CleanEvict) return false;
 127
 128     if (onMiss) {
 129         return !inCache(addr, is_secure) &&
 130                !inMissQueue(addr, is_secure);
 131     }
 132
 133     return true;
 134 }
 135
 136 bool
 137 BasePrefetcher::inCache(Addr addr, bool is_secure) const
 138 {
 139     return cache->inCache(addr, is_secure);
 140 }
 141
 142 bool
 143 BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
 144 {
 145     return cache->inMissQueue(addr, is_secure);
 146 }
 147
 148 bool
 149 BasePrefetcher::samePage(Addr a, Addr b) const
 150 {
 151     return roundDown(a, pageBytes) == roundDown(b, pageBytes);
 152 }
 153
 154 Addr
 155 BasePrefetcher::blockAddress(Addr a) const
 156 {
 157     return a & ~((Addr)blkSize-1);
 158 }
 159
 160 Addr
 161 BasePrefetcher::blockIndex(Addr a) const
 162 {
 163     return a >> lBlkSize;
 164 }
 165
 166 Addr
 167 BasePrefetcher::pageAddress(Addr a) const
 168 {
 169     return roundDown(a, pageBytes);
 170 }
 171
 172 Addr
 173 BasePrefetcher::pageOffset(Addr a) const
 174 {
 175     return a & (pageBytes - 1);
 176 }
 177
 178 Addr
 179 BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
 180 {
 181     return page + (blockIndex << lBlkSize);
 182 }
 183
 184 void
 185 BasePrefetcher::probeNotify(const PacketPtr &pkt)
 186 {
 187     // Don't notify prefetcher on SWPrefetch, cache maintenance
 188     // operations or for writes that we are coaslescing.
 189     if (pkt->cmd.isSWPrefetch()) return;
 190     if (pkt->req->isCacheMaintenance()) return;
 191     if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
 192
 193     // Verify this access type is observed by prefetcher
 194     if (observeAccess(pkt)) {
 195         if (useVirtualAddresses && pkt->req->hasVaddr()) {
 196             PrefetchInfo pfi(pkt, pkt->req->getVaddr());
 197             notify(pkt, pfi);
 198         } else if (!useVirtualAddresses && pkt->req->hasPaddr()) {
 199             PrefetchInfo pfi(pkt, pkt->req->getPaddr());
 200             notify(pkt, pfi);
 201         }
 202     }
 203 }
 204
 205 void
 206 BasePrefetcher::regProbeListeners()
 207 {
 208     /**
 209      * If no probes were added by the configuration scripts, connect to the
 210      * parent cache using the probe "Miss". Also connect to "Hit", if the
 211      * cache is configured to prefetch on accesses.
 212      */
 213     if (listeners.empty() && cache != nullptr) {
 214         ProbeManager *pm(cache->getProbeManager());
 215         listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
 216         if (prefetchOnAccess) {
 217             listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
 218         }
 219     }
 220 }
 221
 222 void
 223 BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
 224 {
 225     ProbeManager *pm(obj->getProbeManager());
 226     listeners.push_back(new PrefetchListener(*this, pm, name));
 227 }