src/mem/cache/prefetch/base.cc

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Mitch Hayenga
  42  */
  43
  44 /**
  45  * @file
  46  * Hardware Prefetcher Definition.
  47  */
  48
  49 #include "mem/cache/prefetch/base.hh"
  50
  51 #include <cassert>
  52
  53 #include "base/intmath.hh"
  54 #include "cpu/base.hh"
  55 #include "mem/cache/base.hh"
  56 #include "params/BasePrefetcher.hh"
  57 #include "sim/system.hh"
  58
  59 void
  60 BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
  61 {
  62     parent.probeNotify(pkt);
  63 }
  64
  65 BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
  66     : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
  67       lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
  68       onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
  69       masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
  70       prefetchOnAccess(p->prefetch_on_access)
  71 {
  72 }
  73
  74 void
  75 BasePrefetcher::setCache(BaseCache *_cache)
  76 {
  77     assert(!cache);
  78     cache = _cache;
  79
  80     // If the cache has a different block size from the system's, save it
  81     blkSize = cache->getBlockSize();
  82     lBlkSize = floorLog2(blkSize);
  83 }
  84
  85 void
  86 BasePrefetcher::regStats()
  87 {
  88     ClockedObject::regStats();
  89
  90     pfIssued
  91         .name(name() + ".num_hwpf_issued")
  92         .desc("number of hwpf issued")
  93         ;
  94
  95 }
  96
  97 bool
  98 BasePrefetcher::observeAccess(const PacketPtr &pkt) const
  99 {
 100     Addr addr = pkt->getAddr();
 101     bool fetch = pkt->req->isInstFetch();
 102     bool read = pkt->isRead();
 103     bool inv = pkt->isInvalidate();
 104     bool is_secure = pkt->isSecure();
 105
 106     if (pkt->req->isUncacheable()) return false;
 107     if (fetch && !onInst) return false;
 108     if (!fetch && !onData) return false;
 109     if (!fetch && read && !onRead) return false;
 110     if (!fetch && !read && !onWrite) return false;
 111     if (!fetch && !read && inv) return false;
 112     if (pkt->cmd == MemCmd::CleanEvict) return false;
 113
 114     if (onMiss) {
 115         return !inCache(addr, is_secure) &&
 116                !inMissQueue(addr, is_secure);
 117     }
 118
 119     return true;
 120 }
 121
 122 bool
 123 BasePrefetcher::inCache(Addr addr, bool is_secure) const
 124 {
 125     return cache->inCache(addr, is_secure);
 126 }
 127
 128 bool
 129 BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
 130 {
 131     return cache->inMissQueue(addr, is_secure);
 132 }
 133
 134 bool
 135 BasePrefetcher::samePage(Addr a, Addr b) const
 136 {
 137     return roundDown(a, pageBytes) == roundDown(b, pageBytes);
 138 }
 139
 140 Addr
 141 BasePrefetcher::blockAddress(Addr a) const
 142 {
 143     return a & ~(blkSize-1);
 144 }
 145
 146 Addr
 147 BasePrefetcher::blockIndex(Addr a) const
 148 {
 149     return a >> lBlkSize;
 150 }
 151
 152 Addr
 153 BasePrefetcher::pageAddress(Addr a) const
 154 {
 155     return roundDown(a, pageBytes);
 156 }
 157
 158 Addr
 159 BasePrefetcher::pageOffset(Addr a) const
 160 {
 161     return a & (pageBytes - 1);
 162 }
 163
 164 Addr
 165 BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
 166 {
 167     return page + (blockIndex << lBlkSize);
 168 }
 169
 170 void
 171 BasePrefetcher::probeNotify(const PacketPtr &pkt)
 172 {
 173     // Don't notify prefetcher on SWPrefetch, cache maintenance
 174     // operations or for writes that we are coaslescing.
 175     if (pkt->cmd.isSWPrefetch()) return;
 176     if (pkt->req->isCacheMaintenance()) return;
 177     if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
 178     notify(pkt);
 179 }
 180
 181 void
 182 BasePrefetcher::regProbeListeners()
 183 {
 184     /**
 185      * If no probes were added by the configuration scripts, connect to the
 186      * parent cache using the probe "Miss". Also connect to "Hit", if the
 187      * cache is configured to prefetch on accesses.
 188      */
 189     if (listeners.empty() && cache != nullptr) {
 190         ProbeManager *pm(cache->getProbeManager());
 191         listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
 192         if (prefetchOnAccess) {
 193             listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
 194         }
 195     }
 196 }
 197
 198 void
 199 BasePrefetcher::addEventProbe(SimObject *obj, const char *name)
 200 {
 201     ProbeManager *pm(obj->getProbeManager());
 202     listeners.push_back(new PrefetchListener(*this, pm, name));
 203 }