src/mem/cache/prefetch/base.hh

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /**
  42  * @file
  43  * Miss and writeback queue declarations.
  44  */
  45
  46 #ifndef __MEM_CACHE_PREFETCH_BASE_HH__
  47 #define __MEM_CACHE_PREFETCH_BASE_HH__
  48
  49 #include <cstdint>
  50
  51 #include "arch/generic/tlb.hh"
  52 #include "base/statistics.hh"
  53 #include "base/types.hh"
  54 #include "mem/packet.hh"
  55 #include "mem/request.hh"
  56 #include "sim/byteswap.hh"
  57 #include "sim/clocked_object.hh"
  58 #include "sim/probe/probe.hh"
  59
  60 class BaseCache;
  61 struct BasePrefetcherParams;
  62
  63 namespace Prefetcher {
  64
  65 class Base : public ClockedObject
  66 {
  67     class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
  68     {
  69       public:
  70         PrefetchListener(Base &_parent, ProbeManager *pm,
  71                          const std::string &name, bool _isFill = false,
  72                          bool _miss = false)
  73             : ProbeListenerArgBase(pm, name),
  74               parent(_parent), isFill(_isFill), miss(_miss) {}
  75         void notify(const PacketPtr &pkt) override;
  76       protected:
  77         Base &parent;
  78         const bool isFill;
  79         const bool miss;
  80     };
  81
  82     std::vector<PrefetchListener *> listeners;
  83
  84   public:
  85
  86     /**
  87      * Class containing the information needed by the prefetch to train and
  88      * generate new prefetch requests.
  89      */
  90     class PrefetchInfo {
  91         /** The address used to train and generate prefetches */
  92         Addr address;
  93         /** The program counter that generated this address. */
  94         Addr pc;
  95         /** The requestor ID that generated this address. */
  96         MasterID masterId;
  97         /** Validity bit for the PC of this address. */
  98         bool validPC;
  99         /** Whether this address targets the secure memory space. */
 100         bool secure;
 101         /** Size in bytes of the request triggering this event */
 102         unsigned int size;
 103         /** Whether this event comes from a write request */
 104         bool write;
 105         /** Physical address, needed because address can be virtual */
 106         Addr paddress;
 107         /** Whether this event comes from a cache miss */
 108         bool cacheMiss;
 109         /** Pointer to the associated request data */
 110         uint8_t *data;
 111
 112       public:
 113         /**
 114          * Obtains the address value of this Prefetcher address.
 115          * @return the addres value.
 116          */
 117         Addr getAddr() const
 118         {
 119             return address;
 120         }
 121
 122         /**
 123          * Returns true if the address targets the secure memory space.
 124          * @return true if the address targets the secure memory space.
 125          */
 126         bool isSecure() const
 127         {
 128             return secure;
 129         }
 130
 131         /**
 132          * Returns the program counter that generated this request.
 133          * @return the pc value
 134          */
 135         Addr getPC() const
 136         {
 137             assert(hasPC());
 138             return pc;
 139         }
 140
 141         /**
 142          * Returns true if the associated program counter is valid
 143          * @return true if the program counter has a valid value
 144          */
 145         bool hasPC() const
 146         {
 147             return validPC;
 148         }
 149
 150         /**
 151          * Gets the requestor ID that generated this address
 152          * @return the requestor ID that generated this address
 153          */
 154         MasterID getMasterId() const
 155         {
 156             return masterId;
 157         }
 158
 159         /**
 160          * Gets the size of the request triggering this event
 161          * @return the size in bytes of the request triggering this event
 162          */
 163         unsigned int getSize() const
 164         {
 165             return size;
 166         }
 167
 168         /**
 169          * Checks if the request that caused this prefetch event was a write
 170          * request
 171          * @return true if the request causing this event is a write request
 172          */
 173         bool isWrite() const
 174         {
 175             return write;
 176         }
 177
 178         /**
 179          * Gets the physical address of the request
 180          * @return physical address of the request
 181          */
 182         Addr getPaddr() const
 183         {
 184             return paddress;
 185         }
 186
 187         /**
 188          * Check if this event comes from a cache miss
 189          * @result true if this event comes from a cache miss
 190          */
 191         bool isCacheMiss() const
 192         {
 193             return cacheMiss;
 194         }
 195
 196         /**
 197          * Gets the associated data of the request triggering the event
 198          * @param Byte ordering of the stored data
 199          * @return the data
 200          */
 201         template <typename T>
 202         inline T
 203         get(ByteOrder endian) const
 204         {
 205             if (data == nullptr) {
 206                 panic("PrefetchInfo::get called with a request with no data.");
 207             }
 208             switch (endian) {
 209                 case ByteOrder::big:
 210                     return betoh(*(T*)data);
 211
 212                 case ByteOrder::little:
 213                     return letoh(*(T*)data);
 214
 215                 default:
 216                     panic("Illegal byte order in PrefetchInfo::get()\n");
 217             };
 218         }
 219
 220         /**
 221          * Check for equality
 222          * @param pfi PrefetchInfo to compare against
 223          * @return True if this object and the provided one are equal
 224          */
 225         bool sameAddr(PrefetchInfo const &pfi) const
 226         {
 227             return this->getAddr() == pfi.getAddr() &&
 228                 this->isSecure() == pfi.isSecure();
 229         }
 230
 231         /**
 232          * Constructs a PrefetchInfo using a PacketPtr.
 233          * @param pkt PacketPtr used to generate the PrefetchInfo
 234          * @param addr the address value of the new object, this address is
 235          *        used to train the prefetcher
 236          * @param miss whether this event comes from a cache miss
 237          */
 238         PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
 239
 240         /**
 241          * Constructs a PrefetchInfo using a new address value and
 242          * another PrefetchInfo as a reference.
 243          * @param pfi PrefetchInfo used to generate this new object
 244          * @param addr the address value of the new object
 245          */
 246         PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
 247
 248         ~PrefetchInfo()
 249         {
 250             delete[] data;
 251         }
 252     };
 253
 254   protected:
 255
 256     // PARAMETERS
 257
 258     /** Pointr to the parent cache. */
 259     BaseCache* cache;
 260
 261     /** The block size of the parent cache. */
 262     unsigned blkSize;
 263
 264     /** log_2(block size of the parent cache). */
 265     unsigned lBlkSize;
 266
 267     /** Only consult prefetcher on cache misses? */
 268     const bool onMiss;
 269
 270     /** Consult prefetcher on reads? */
 271     const bool onRead;
 272
 273     /** Consult prefetcher on reads? */
 274     const bool onWrite;
 275
 276     /** Consult prefetcher on data accesses? */
 277     const bool onData;
 278
 279     /** Consult prefetcher on instruction accesses? */
 280     const bool onInst;
 281
 282     /** Request id for prefetches */
 283     const MasterID masterId;
 284
 285     const Addr pageBytes;
 286
 287     /** Prefetch on every access, not just misses */
 288     const bool prefetchOnAccess;
 289
 290     /** Use Virtual Addresses for prefetching */
 291     const bool useVirtualAddresses;
 292
 293     /**
 294      * Determine if this access should be observed
 295      * @param pkt The memory request causing the event
 296      * @param miss whether this event comes from a cache miss
 297      */
 298     bool observeAccess(const PacketPtr &pkt, bool miss) const;
 299
 300     /** Determine if address is in cache */
 301     bool inCache(Addr addr, bool is_secure) const;
 302
 303     /** Determine if address is in cache miss queue */
 304     bool inMissQueue(Addr addr, bool is_secure) const;
 305
 306     bool hasBeenPrefetched(Addr addr, bool is_secure) const;
 307
 308     /** Determine if addresses are on the same page */
 309     bool samePage(Addr a, Addr b) const;
 310     /** Determine the address of the block in which a lays */
 311     Addr blockAddress(Addr a) const;
 312     /** Determine the address of a at block granularity */
 313     Addr blockIndex(Addr a) const;
 314     /** Determine the address of the page in which a lays */
 315     Addr pageAddress(Addr a) const;
 316     /** Determine the page-offset of a  */
 317     Addr pageOffset(Addr a) const;
 318     /** Build the address of the i-th block inside the page */
 319     Addr pageIthBlockAddress(Addr page, uint32_t i) const;
 320     struct StatGroup : public Stats::Group
 321     {
 322         StatGroup(Stats::Group *parent);
 323         Stats::Scalar pfIssued;
 324     } prefetchStats;
 325
 326     /** Total prefetches issued */
 327     uint64_t issuedPrefetches;
 328     /** Total prefetches that has been useful */
 329     uint64_t usefulPrefetches;
 330
 331     /** Registered tlb for address translations */
 332     BaseTLB * tlb;
 333
 334   public:
 335     Base(const BasePrefetcherParams *p);
 336     virtual ~Base() = default;
 337
 338     virtual void setCache(BaseCache *_cache);
 339
 340     /**
 341      * Notify prefetcher of cache access (may be any access or just
 342      * misses, depending on cache parameters.)
 343      */
 344     virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;
 345
 346     /** Notify prefetcher of cache fill */
 347     virtual void notifyFill(const PacketPtr &pkt)
 348     {}
 349
 350     virtual PacketPtr getPacket() = 0;
 351
 352     virtual Tick nextPrefetchReadyTime() const = 0;
 353
 354
 355     /**
 356      * Register probe points for this object.
 357      */
 358     void regProbeListeners() override;
 359
 360     /**
 361      * Process a notification event from the ProbeListener.
 362      * @param pkt The memory request causing the event
 363      * @param miss whether this event comes from a cache miss
 364      */
 365     void probeNotify(const PacketPtr &pkt, bool miss);
 366
 367     /**
 368      * Add a SimObject and a probe name to listen events from
 369      * @param obj The SimObject pointer to listen from
 370      * @param name The probe name
 371      */
 372     void addEventProbe(SimObject *obj, const char *name);
 373
 374     /**
 375      * Add a BaseTLB object to be used whenever a translation is needed.
 376      * This is generally required when the prefetcher is allowed to generate
 377      * page crossing references and/or uses virtual addresses for training.
 378      * @param tlb pointer to the BaseTLB object to add
 379      */
 380     void addTLB(BaseTLB *tlb);
 381 };
 382
 383 } // namespace Prefetcher
 384
 385 #endif //__MEM_CACHE_PREFETCH_BASE_HH__