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14 * Copyright (c) 2005 The Regents of The University of Michigan
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40 * Authors: Ron Dreslinski
46 * Miss and writeback queue declarations.
49 #ifndef __MEM_CACHE_PREFETCH_BASE_HH__
50 #define __MEM_CACHE_PREFETCH_BASE_HH__
54 #include "base/statistics.hh"
55 #include "base/types.hh"
56 #include "mem/packet.hh"
57 #include "mem/request.hh"
58 #include "sim/clocked_object.hh"
61 struct BasePrefetcherParams;
64 class BasePrefetcher : public ClockedObject
70 /** Pointr to the parent cache. */
73 /** The block size of the parent cache. */
76 /** log_2(block size of the parent cache). */
79 /** System we belong to */
82 /** Only consult prefetcher on cache misses? */
85 /** Consult prefetcher on reads? */
88 /** Consult prefetcher on reads? */
91 /** Consult prefetcher on data accesses? */
94 /** Consult prefetcher on instruction accesses? */
97 /** Request id for prefetches */
100 const Addr pageBytes;
102 /** Determine if this access should be observed */
103 bool observeAccess(const PacketPtr &pkt) const;
105 /** Determine if address is in cache */
106 bool inCache(Addr addr, bool is_secure) const;
108 /** Determine if address is in cache miss queue */
109 bool inMissQueue(Addr addr, bool is_secure) const;
111 /** Determine if addresses are on the same page */
112 bool samePage(Addr a, Addr b) const;
113 /** Determine the address of the block in which a lays */
114 Addr blockAddress(Addr a) const;
115 /** Determine the address of a at block granularity */
116 Addr blockIndex(Addr a) const;
117 /** Determine the address of the page in which a lays */
118 Addr pageAddress(Addr a) const;
119 /** Determine the page-offset of a */
120 Addr pageOffset(Addr a) const;
121 /** Build the address of the i-th block inside the page */
122 Addr pageIthBlockAddress(Addr page, uint32_t i) const;
125 Stats::Scalar pfIssued;
129 BasePrefetcher(const BasePrefetcherParams *p);
131 virtual ~BasePrefetcher() {}
133 virtual void setCache(BaseCache *_cache);
136 * Notify prefetcher of cache access (may be any access or just
137 * misses, depending on cache parameters.)
138 * @retval Time of next prefetch availability, or MaxTick if none.
140 virtual Tick notify(const PacketPtr &pkt) = 0;
142 virtual PacketPtr getPacket() = 0;
144 virtual Tick nextPrefetchReadyTime() const = 0;
146 virtual void regStats();
148 #endif //__MEM_CACHE_PREFETCH_BASE_HH__