src/mem/cache/prefetch/base.hh

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ron Dreslinski
  41  *          Mitch Hayenga
  42  */
  43
  44 /**
  45  * @file
  46  * Miss and writeback queue declarations.
  47  */
  48
  49 #ifndef __MEM_CACHE_PREFETCH_BASE_HH__
  50 #define __MEM_CACHE_PREFETCH_BASE_HH__
  51
  52 #include <cstdint>
  53
  54 #include "arch/isa_traits.hh"
  55 #include "arch/generic/tlb.hh"
  56 #include "base/statistics.hh"
  57 #include "base/types.hh"
  58 #include "mem/packet.hh"
  59 #include "mem/request.hh"
  60 #include "sim/byteswap.hh"
  61 #include "sim/clocked_object.hh"
  62 #include "sim/probe/probe.hh"
  63
  64 class BaseCache;
  65 struct BasePrefetcherParams;
  66
  67 class BasePrefetcher : public ClockedObject
  68 {
  69     class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
  70     {
  71       public:
  72         PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
  73                          const std::string &name, bool _isFill = false,
  74                          bool _miss = false)
  75             : ProbeListenerArgBase(pm, name),
  76               parent(_parent), isFill(_isFill), miss(_miss) {}
  77         void notify(const PacketPtr &pkt) override;
  78       protected:
  79         BasePrefetcher &parent;
  80         const bool isFill;
  81         const bool miss;
  82     };
  83
  84     std::vector<PrefetchListener *> listeners;
  85
  86   public:
  87
  88     /**
  89      * Class containing the information needed by the prefetch to train and
  90      * generate new prefetch requests.
  91      */
  92     class PrefetchInfo {
  93         /** The address used to train and generate prefetches */
  94         Addr address;
  95         /** The program counter that generated this address. */
  96         Addr pc;
  97         /** The requestor ID that generated this address. */
  98         MasterID masterId;
  99         /** Validity bit for the PC of this address. */
 100         bool validPC;
 101         /** Whether this address targets the secure memory space. */
 102         bool secure;
 103         /** Size in bytes of the request triggering this event */
 104         unsigned int size;
 105         /** Whether this event comes from a write request */
 106         bool write;
 107         /** Physical address, needed because address can be virtual */
 108         Addr paddress;
 109         /** Whether this event comes from a cache miss */
 110         bool cacheMiss;
 111         /** Pointer to the associated request data */
 112         uint8_t *data;
 113
 114       public:
 115         /**
 116          * Obtains the address value of this Prefetcher address.
 117          * @return the addres value.
 118          */
 119         Addr getAddr() const
 120         {
 121             return address;
 122         }
 123
 124         /**
 125          * Returns true if the address targets the secure memory space.
 126          * @return true if the address targets the secure memory space.
 127          */
 128         bool isSecure() const
 129         {
 130             return secure;
 131         }
 132
 133         /**
 134          * Returns the program counter that generated this request.
 135          * @return the pc value
 136          */
 137         Addr getPC() const
 138         {
 139             assert(hasPC());
 140             return pc;
 141         }
 142
 143         /**
 144          * Returns true if the associated program counter is valid
 145          * @return true if the program counter has a valid value
 146          */
 147         bool hasPC() const
 148         {
 149             return validPC;
 150         }
 151
 152         /**
 153          * Gets the requestor ID that generated this address
 154          * @return the requestor ID that generated this address
 155          */
 156         MasterID getMasterId() const
 157         {
 158             return masterId;
 159         }
 160
 161         /**
 162          * Gets the size of the request triggering this event
 163          * @return the size in bytes of the request triggering this event
 164          */
 165         unsigned int getSize() const
 166         {
 167             return size;
 168         }
 169
 170         /**
 171          * Checks if the request that caused this prefetch event was a write
 172          * request
 173          * @return true if the request causing this event is a write request
 174          */
 175         bool isWrite() const
 176         {
 177             return write;
 178         }
 179
 180         /**
 181          * Gets the physical address of the request
 182          * @return physical address of the request
 183          */
 184         Addr getPaddr() const
 185         {
 186             return paddress;
 187         }
 188
 189         /**
 190          * Check if this event comes from a cache miss
 191          * @result true if this event comes from a cache miss
 192          */
 193         bool isCacheMiss() const
 194         {
 195             return cacheMiss;
 196         }
 197
 198         /**
 199          * Gets the associated data of the request triggering the event
 200          * @param Byte ordering of the stored data
 201          * @return the data
 202          */
 203         template <typename T>
 204         inline T
 205         get(ByteOrder endian) const
 206         {
 207             if (data == nullptr) {
 208                 panic("PrefetchInfo::get called with a request with no data.");
 209             }
 210             switch (endian) {
 211                 case BigEndianByteOrder:
 212                     return betoh(*(T*)data);
 213
 214                 case LittleEndianByteOrder:
 215                     return letoh(*(T*)data);
 216
 217                 default:
 218                     panic("Illegal byte order in PrefetchInfo::get()\n");
 219             };
 220         }
 221
 222         /**
 223          * Check for equality
 224          * @param pfi PrefetchInfo to compare against
 225          * @return True if this object and the provided one are equal
 226          */
 227         bool sameAddr(PrefetchInfo const &pfi) const
 228         {
 229             return this->getAddr() == pfi.getAddr() &&
 230                 this->isSecure() == pfi.isSecure();
 231         }
 232
 233         /**
 234          * Constructs a PrefetchInfo using a PacketPtr.
 235          * @param pkt PacketPtr used to generate the PrefetchInfo
 236          * @param addr the address value of the new object, this address is
 237          *        used to train the prefetcher
 238          * @param miss whether this event comes from a cache miss
 239          */
 240         PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
 241
 242         /**
 243          * Constructs a PrefetchInfo using a new address value and
 244          * another PrefetchInfo as a reference.
 245          * @param pfi PrefetchInfo used to generate this new object
 246          * @param addr the address value of the new object
 247          */
 248         PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
 249
 250         ~PrefetchInfo()
 251         {
 252             delete data;
 253         }
 254     };
 255
 256   protected:
 257
 258     // PARAMETERS
 259
 260     /** Pointr to the parent cache. */
 261     BaseCache* cache;
 262
 263     /** The block size of the parent cache. */
 264     unsigned blkSize;
 265
 266     /** log_2(block size of the parent cache). */
 267     unsigned lBlkSize;
 268
 269     /** Only consult prefetcher on cache misses? */
 270     const bool onMiss;
 271
 272     /** Consult prefetcher on reads? */
 273     const bool onRead;
 274
 275     /** Consult prefetcher on reads? */
 276     const bool onWrite;
 277
 278     /** Consult prefetcher on data accesses? */
 279     const bool onData;
 280
 281     /** Consult prefetcher on instruction accesses? */
 282     const bool onInst;
 283
 284     /** Request id for prefetches */
 285     const MasterID masterId;
 286
 287     const Addr pageBytes;
 288
 289     /** Prefetch on every access, not just misses */
 290     const bool prefetchOnAccess;
 291
 292     /** Use Virtual Addresses for prefetching */
 293     const bool useVirtualAddresses;
 294
 295     /**
 296      * Determine if this access should be observed
 297      * @param pkt The memory request causing the event
 298      * @param miss whether this event comes from a cache miss
 299      */
 300     bool observeAccess(const PacketPtr &pkt, bool miss) const;
 301
 302     /** Determine if address is in cache */
 303     bool inCache(Addr addr, bool is_secure) const;
 304
 305     /** Determine if address is in cache miss queue */
 306     bool inMissQueue(Addr addr, bool is_secure) const;
 307
 308     bool hasBeenPrefetched(Addr addr, bool is_secure) const;
 309
 310     /** Determine if addresses are on the same page */
 311     bool samePage(Addr a, Addr b) const;
 312     /** Determine the address of the block in which a lays */
 313     Addr blockAddress(Addr a) const;
 314     /** Determine the address of a at block granularity */
 315     Addr blockIndex(Addr a) const;
 316     /** Determine the address of the page in which a lays */
 317     Addr pageAddress(Addr a) const;
 318     /** Determine the page-offset of a  */
 319     Addr pageOffset(Addr a) const;
 320     /** Build the address of the i-th block inside the page */
 321     Addr pageIthBlockAddress(Addr page, uint32_t i) const;
 322
 323     Stats::Scalar pfIssued;
 324
 325     /** Total prefetches issued */
 326     uint64_t issuedPrefetches;
 327     /** Total prefetches that has been useful */
 328     uint64_t usefulPrefetches;
 329
 330     /** Registered tlb for address translations */
 331     BaseTLB * tlb;
 332
 333   public:
 334
 335     BasePrefetcher(const BasePrefetcherParams *p);
 336
 337     virtual ~BasePrefetcher() {}
 338
 339     virtual void setCache(BaseCache *_cache);
 340
 341     /**
 342      * Notify prefetcher of cache access (may be any access or just
 343      * misses, depending on cache parameters.)
 344      */
 345     virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;
 346
 347     /** Notify prefetcher of cache fill */
 348     virtual void notifyFill(const PacketPtr &pkt)
 349     {}
 350
 351     virtual PacketPtr getPacket() = 0;
 352
 353     virtual Tick nextPrefetchReadyTime() const = 0;
 354
 355     /**
 356      * Register local statistics.
 357      */
 358     void regStats() override;
 359
 360     /**
 361      * Register probe points for this object.
 362      */
 363     void regProbeListeners() override;
 364
 365     /**
 366      * Process a notification event from the ProbeListener.
 367      * @param pkt The memory request causing the event
 368      * @param miss whether this event comes from a cache miss
 369      */
 370     void probeNotify(const PacketPtr &pkt, bool miss);
 371
 372     /**
 373      * Add a SimObject and a probe name to listen events from
 374      * @param obj The SimObject pointer to listen from
 375      * @param name The probe name
 376      */
 377     void addEventProbe(SimObject *obj, const char *name);
 378
 379     /**
 380      * Add a BaseTLB object to be used whenever a translation is needed.
 381      * This is generally required when the prefetcher is allowed to generate
 382      * page crossing references and/or uses virtual addresses for training.
 383      * @param tlb pointer to the BaseTLB object to add
 384      */
 385     void addTLB(BaseTLB *tlb);
 386 };
 387 #endif //__MEM_CACHE_PREFETCH_BASE_HH__