src/mem/cache/prefetch/base_prefetcher.hh

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ron Dreslinski
  29  */
  30
  31 /**
  32  * @file
  33  * Miss and writeback queue declarations.
  34  */
  35
  36 #ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
  37 #define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
  38
  39 #include "mem/packet.hh"
  40 #include <list>
  41
  42 class BaseCache;
  43 class BasePrefetcher
  44 {
  45   protected:
  46
  47     /** The Prefetch Queue. */
  48     std::list<PacketPtr> pf;
  49
  50     // PARAMETERS
  51
  52     /** The number of MSHRs in the Prefetch Queue. */
  53     const int size;
  54
  55     /** Pointr to the parent cache. */
  56     BaseCache* cache;
  57
  58     /** The block size of the parent cache. */
  59     int blkSize;
  60
  61     /** Do we prefetch across page boundaries. */
  62     bool pageStop;
  63
  64     /** Do we remove prefetches with later times than a new miss.*/
  65     bool serialSquash;
  66
  67     /** Do we check if it is in the cache when inserting into buffer,
  68         or removing.*/
  69     bool cacheCheckPush;
  70
  71     /** Do we prefetch on only data reads, or on inst reads as well. */
  72     bool only_data;
  73
  74   public:
  75
  76     Stats::Scalar<> pfIdentified;
  77     Stats::Scalar<> pfMSHRHit;
  78     Stats::Scalar<> pfCacheHit;
  79     Stats::Scalar<> pfBufferHit;
  80     Stats::Scalar<> pfRemovedFull;
  81     Stats::Scalar<> pfRemovedMSHR;
  82     Stats::Scalar<> pfIssued;
  83     Stats::Scalar<> pfSpanPage;
  84     Stats::Scalar<> pfSquashed;
  85
  86     void regStats(const std::string &name);
  87
  88   public:
  89     BasePrefetcher(int numMSHRS, bool pageStop, bool serialSquash,
  90                    bool cacheCheckPush, bool onlyData);
  91
  92     virtual ~BasePrefetcher() {}
  93
  94     void setCache(BaseCache *_cache);
  95
  96     void handleMiss(PacketPtr &pkt, Tick time);
  97
  98     PacketPtr getPacket();
  99
 100     bool havePending()
 101     {
 102         return !pf.empty();
 103     }
 104
 105     virtual void calculatePrefetch(PacketPtr &pkt,
 106                                    std::list<Addr> &addresses,
 107                                    std::list<Tick> &delays) = 0;
 108
 109     virtual bool inCache(PacketPtr &pkt) = 0;
 110
 111     virtual bool inMissQueue(Addr address) = 0;
 112
 113     std::list<PacketPtr>::iterator inPrefetch(Addr address);
 114 };
 115
 116
 117 #endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__