2 * Copyright (c) 2005 The Regents of The University of Michigan
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28 * Authors: Ron Dreslinski
33 * Miss and writeback queue declarations.
36 #ifndef __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
37 #define __MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__
39 #include "mem/packet.hh"
47 /** The Prefetch Queue. */
48 std::list<PacketPtr> pf;
52 /** The number of MSHRs in the Prefetch Queue. */
55 /** Pointr to the parent cache. */
58 /** The block size of the parent cache. */
61 /** Do we prefetch across page boundaries. */
64 /** Do we remove prefetches with later times than a new miss.*/
67 /** Do we check if it is in the cache when inserting into buffer,
71 /** Do we prefetch on only data reads, or on inst reads as well. */
76 Stats::Scalar<> pfIdentified;
77 Stats::Scalar<> pfMSHRHit;
78 Stats::Scalar<> pfCacheHit;
79 Stats::Scalar<> pfBufferHit;
80 Stats::Scalar<> pfRemovedFull;
81 Stats::Scalar<> pfRemovedMSHR;
82 Stats::Scalar<> pfIssued;
83 Stats::Scalar<> pfSpanPage;
84 Stats::Scalar<> pfSquashed;
86 void regStats(const std::string &name);
89 BasePrefetcher(int numMSHRS, bool pageStop, bool serialSquash,
90 bool cacheCheckPush, bool onlyData);
92 virtual ~BasePrefetcher() {}
94 void setCache(BaseCache *_cache);
96 void handleMiss(PacketPtr &pkt, Tick time);
98 PacketPtr getPacket();
105 virtual void calculatePrefetch(PacketPtr &pkt,
106 std::list<Addr> &addresses,
107 std::list<Tick> &delays) = 0;
109 virtual bool inCache(PacketPtr &pkt) = 0;
111 virtual bool inMissQueue(Addr address) = 0;
113 std::list<PacketPtr>::iterator inPrefetch(Addr address);
117 #endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__