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28 * Authors: Ron Dreslinski
33 * Describes a ghb prefetcher based on template policies.
36 #ifndef __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
37 #define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
39 #include "base/misc.hh" // fatal, panic, and warn
41 #include "mem/cache/prefetch/prefetcher.hh"
44 * A template-policy based cache. The behavior of the cache can be altered by
45 * supplying different template policies. TagStore handles all tag and data
46 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
47 * @sa MissQueue. Coherence handles all coherence policy details @sa
48 * UniCoherence, SimpleMultiCoherence.
50 template <class TagStore, class Buffering>
51 class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
58 Addr second_last_miss_addr[64/*MAX_CPUS*/];
59 Addr last_miss_addr[64/*MAX_CPUS*/];
67 GHBPrefetcher(int size, bool pageStop, bool serialSquash,
68 bool cacheCheckPush, bool onlyData,
69 Tick latency, int degree, bool useCPUId)
70 :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
71 cacheCheckPush, onlyData),
72 latency(latency), degree(degree), useCPUId(useCPUId)
78 void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
79 std::list<Tick> &delays)
81 Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
82 int cpuID = pkt->req->getCpuNum();
83 if (!useCPUId) cpuID = 0;
86 int new_stride = blkAddr - last_miss_addr[cpuID];
87 int old_stride = last_miss_addr[cpuID] -
88 second_last_miss_addr[cpuID];
90 second_last_miss_addr[cpuID] = last_miss_addr[cpuID];
91 last_miss_addr[cpuID] = blkAddr;
93 if (new_stride == old_stride) {
94 for (int d=1; d <= degree; d++) {
95 Addr newAddr = blkAddr + d * new_stride;
97 (blkAddr & ~(TheISA::VMPageSize - 1)) !=
98 (newAddr & ~(TheISA::VMPageSize - 1)))
100 //Spanned the page, so now stop
101 this->pfSpanPage += degree - d + 1;
106 addresses.push_back(newAddr);
107 delays.push_back(latency);
114 #endif // __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__