src/mem/cache/prefetch/ghb_prefetcher.hh

   1 /*
   2  * Copyright (c) 2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ron Dreslinski
  29  */
  30
  31 /**
  32  * @file
  33  * Describes a ghb prefetcher based on template policies.
  34  */
  35
  36 #ifndef __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
  37 #define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
  38
  39 #include "base/misc.hh" // fatal, panic, and warn
  40
  41 #include "mem/cache/prefetch/prefetcher.hh"
  42
  43 /**
  44  * A template-policy based cache. The behavior of the cache can be altered by
  45  * supplying different template policies. TagStore handles all tag and data
  46  * storage @sa TagStore. Buffering handles all misses and writes/writebacks
  47  * @sa MissQueue. Coherence handles all coherence policy details @sa
  48  * UniCoherence, SimpleMultiCoherence.
  49  */
  50 template <class TagStore, class Buffering>
  51 class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
  52 {
  53   protected:
  54
  55     Buffering* mq;
  56     TagStore* tags;
  57
  58     Addr second_last_miss_addr[64/*MAX_CPUS*/];
  59     Addr last_miss_addr[64/*MAX_CPUS*/];
  60
  61     Tick latency;
  62     int degree;
  63     bool useCPUId;
  64
  65   public:
  66
  67     GHBPrefetcher(int size, bool pageStop, bool serialSquash,
  68                   bool cacheCheckPush, bool onlyData,
  69                   Tick latency, int degree, bool useCPUId)
  70         :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
  71                                          cacheCheckPush, onlyData),
  72          latency(latency), degree(degree), useCPUId(useCPUId)
  73     {
  74     }
  75
  76     ~GHBPrefetcher() {}
  77
  78     void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses,
  79                            std::list<Tick> &delays)
  80     {
  81         Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
  82         int cpuID = pkt->req->getCpuNum();
  83         if (!useCPUId) cpuID = 0;
  84
  85
  86         int new_stride = blkAddr - last_miss_addr[cpuID];
  87         int old_stride = last_miss_addr[cpuID] -
  88                          second_last_miss_addr[cpuID];
  89
  90         second_last_miss_addr[cpuID] = last_miss_addr[cpuID];
  91         last_miss_addr[cpuID] = blkAddr;
  92
  93         if (new_stride == old_stride) {
  94             for (int d=1; d <= degree; d++) {
  95                 Addr newAddr = blkAddr + d * new_stride;
  96                 if (this->pageStop &&
  97                     (blkAddr & ~(TheISA::VMPageSize - 1)) !=
  98                     (newAddr & ~(TheISA::VMPageSize - 1)))
  99                 {
 100                     //Spanned the page, so now stop
 101                     this->pfSpanPage += degree - d + 1;
 102                     return;
 103                 }
 104                 else
 105                 {
 106                     addresses.push_back(newAddr);
 107                     delays.push_back(latency);
 108                 }
 109             }
 110         }
 111     }
 112 };
 113
 114 #endif // __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__