2 * Copyright (c) 2005 The Regents of The University of Michigan
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28 * Authors: Ron Dreslinski
33 * Describes a strided prefetcher based on template policies.
36 #ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
37 #define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
39 #include "base/misc.hh" // fatal, panic, and warn
41 #include "mem/cache/prefetch/prefetcher.hh"
44 * A template-policy based cache. The behavior of the cache can be altered by
45 * supplying different template policies. TagStore handles all tag and data
46 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
47 * @sa MissQueue. Coherence handles all coherence policy details @sa
48 * UniCoherence, SimpleMultiCoherence.
50 template <class TagStore, class Buffering>
51 class StridePrefetcher : public Prefetcher<TagStore, Buffering>
66 /* bool operator < (strideEntry a,strideEntry b)
68 if (a.confidence == b.confidence) {
71 else return a.confidence < b.confidence;
74 Addr* lastMissAddr[64/*MAX_CPUS*/];
76 std::list<strideEntry*> table[64/*MAX_CPUS*/];
84 StridePrefetcher(int size, bool pageStop, bool serialSquash,
85 bool cacheCheckPush, bool onlyData,
86 Tick latency, int degree, bool useCPUId)
87 :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
88 cacheCheckPush, onlyData),
89 latency(latency), degree(degree), useCPUId(useCPUId)
93 ~StridePrefetcher() {}
95 void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
96 std::list<Tick> &delays)
98 // Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
99 int cpuID = pkt->req->getCpuNum();
100 if (!useCPUId) cpuID = 0;
102 /* Scan Table for IAddr Match */
103 /* std::list<strideEntry*>::iterator iter;
104 for (iter=table[cpuID].begin();
105 iter !=table[cpuID].end();
107 if ((*iter)->IAddr == pkt->pc) break;
110 if (iter != table[cpuID].end()) {
113 int newStride = blkAddr - (*iter)->MAddr;
114 if (newStride == (*iter)->stride) {
115 (*iter)->confidence++;
118 (*iter)->stride = newStride;
119 (*iter)->confidence--;
122 (*iter)->MAddr = blkAddr;
124 for (int d=1; d <= degree; d++) {
125 Addr newAddr = blkAddr + d * newStride;
126 if (this->pageStop &&
127 (blkAddr & ~(TheISA::VMPageSize - 1)) !=
128 (newAddr & ~(TheISA::VMPageSize - 1)))
130 //Spanned the page, so now stop
131 this->pfSpanPage += degree - d + 1;
136 addresses.push_back(newAddr);
137 delays.push_back(latency);
143 //Find lowest confidence and replace
149 #endif // __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__