src/mem/cache/queue_entry.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2015-2016 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
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   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
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  20  * notice, this list of conditions and the following disclaimer;
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  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Andreas Hansson
  42  */
  43
  44 /**
  45  * @file
  46  * Generic queue entry
  47  */
  48
  49 #ifndef __MEM_CACHE_QUEUE_ENTRY_HH__
  50 #define __MEM_CACHE_QUEUE_ENTRY_HH__
  51
  52 #include "base/types.hh"
  53 #include "mem/packet.hh"
  54
  55 class BaseCache;
  56
  57 /**
  58  * A queue entry base class, to be used by both the MSHRs and
  59  * write-queue entries.
  60  */
  61 class QueueEntry : public Packet::SenderState
  62 {
  63
  64     /**
  65      * Consider the Queue a friend to avoid making everything public
  66      */
  67     template <class Entry>
  68     friend class Queue;
  69
  70   protected:
  71
  72     /** Tick when ready to issue */
  73     Tick readyTime;
  74
  75     /** True if the entry is uncacheable */
  76     bool _isUncacheable;
  77
  78   public:
  79     /**
  80      * A queue entry is holding packets that will be serviced as soon as
  81      * resources are available. Since multiple references to the same
  82      * address can arrive while a packet is not serviced, each packet is
  83      * stored in a target containing its availability, order and other info,
  84      * and the queue entry stores these similar targets in a list.
  85      */
  86     class Target {
  87       public:
  88         const Tick recvTime;  //!< Time when request was received (for stats)
  89         const Tick readyTime; //!< Time when request is ready to be serviced
  90         const Counter order;  //!< Global order (for memory consistency mgmt)
  91         const PacketPtr pkt;  //!< Pending request packet.
  92
  93         /**
  94          * Default constructor. Assigns the current tick as the arrival time
  95          * of the packet.
  96          *
  97          * @param _pkt The pending request packet.
  98          * @param ready_time The tick at which the packet will be serviceable.
  99          * @param _order Global order.
 100          */
 101         Target(PacketPtr _pkt, Tick ready_time, Counter _order)
 102             : recvTime(curTick()), readyTime(ready_time), order(_order),
 103               pkt(_pkt)
 104         {}
 105     };
 106
 107     /** True if the entry has been sent downstream. */
 108     bool inService;
 109
 110     /** Order number assigned to disambiguate writes and misses. */
 111     Counter order;
 112
 113     /** Block aligned address. */
 114     Addr blkAddr;
 115
 116     /** Block size of the cache. */
 117     unsigned blkSize;
 118
 119     /** True if the entry targets the secure memory space. */
 120     bool isSecure;
 121
 122     QueueEntry()
 123         : readyTime(0), _isUncacheable(false),
 124           inService(false), order(0), blkAddr(0), blkSize(0), isSecure(false)
 125     {}
 126
 127     bool isUncacheable() const { return _isUncacheable; }
 128
 129     /**
 130      * Check if entry corresponds to the one being looked for.
 131      *
 132      * @param addr Address to match against.
 133      * @param is_secure Whether the target should be in secure space or not.
 134      * @return True if entry matches given information.
 135      */
 136     virtual bool matchBlockAddr(const Addr addr, const bool is_secure)
 137                                                             const = 0;
 138
 139     /**
 140      * Check if entry contains a packet that corresponds to the one being
 141      * looked for.
 142      *
 143      * @param pkt The packet to search for.
 144      * @return True if any of its targets' packets matches the given one.
 145      */
 146     virtual bool matchBlockAddr(const PacketPtr pkt) const = 0;
 147
 148     /**
 149      * Check if given entry's packets conflict with this' entries packets.
 150      *
 151      * @param entry Other entry to compare against.
 152      * @return True if entry matches given information.
 153      */
 154     virtual bool conflictAddr(const QueueEntry* entry) const = 0;
 155
 156     /**
 157      * Send this queue entry as a downstream packet, with the exact
 158      * behaviour depending on the specific entry type.
 159      */
 160     virtual bool sendPacket(BaseCache &cache) = 0;
 161
 162     /**
 163      * Returns a pointer to the first target.
 164      *
 165      * @return A pointer to the first target.
 166      */
 167     virtual Target* getTarget() = 0;
 168 };
 169
 170 #endif // __MEM_CACHE_QUEUE_ENTRY_HH__