2 * Copyright (c) 2013,2016,2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Erik Hallnor
46 * Definitions of BaseTags.
49 #include "mem/cache/tags/base.hh"
53 #include "base/types.hh"
54 #include "mem/cache/base.hh"
55 #include "mem/packet.hh"
56 #include "mem/request.hh"
57 #include "sim/core.hh"
58 #include "sim/sim_exit.hh"
59 #include "sim/system.hh"
61 BaseTags::BaseTags(const Params
*p
)
62 : ClockedObject(p
), blkSize(p
->block_size
), blkMask(blkSize
- 1),
64 lookupLatency(p
->tag_latency
),
65 accessLatency(p
->sequential_access
?
66 p
->tag_latency
+ p
->data_latency
:
67 std::max(p
->tag_latency
, p
->data_latency
)),
69 warmupBound((p
->warmup_percentage
/100.0) * (p
->size
/ p
->block_size
)),
70 warmedUp(false), numBlocks(p
->size
/ p
->block_size
),
71 dataBlks(new uint8_t[p
->size
]) // Allocate data storage in one big chunk
76 BaseTags::setCache(BaseCache
*_cache
)
83 BaseTags::insertBlock(const PacketPtr pkt
, CacheBlk
*blk
)
85 assert(!blk
->isValid());
88 Addr addr
= pkt
->getAddr();
90 // Previous block, if existed, has been removed, and now we have
91 // to insert the new one
93 // Deal with what we are bringing in
94 MasterID master_id
= pkt
->req
->masterId();
95 assert(master_id
< cache
->system
->maxMasters());
96 occupancies
[master_id
]++;
98 // Insert block with tag, src master id and task id
99 blk
->insert(extractTag(addr
), pkt
->isSecure(), master_id
,
102 if (!warmedUp
&& tagsInUse
.value() >= warmupBound
) {
104 warmupCycle
= curTick();
107 // We only need to write into one tag and one data block.
113 BaseTags::cleanupRefsVisitor(CacheBlk
&blk
)
116 totalRefs
+= blk
.refCount
;
122 BaseTags::cleanupRefs()
124 forEachBlk([this](CacheBlk
&blk
) { cleanupRefsVisitor(blk
); });
128 BaseTags::computeStatsVisitor(CacheBlk
&blk
)
131 assert(blk
.task_id
< ContextSwitchTaskId::NumTaskId
);
132 occupanciesTaskId
[blk
.task_id
]++;
133 assert(blk
.tickInserted
<= curTick());
134 Tick age
= curTick() - blk
.tickInserted
;
137 if (age
/ SimClock::Int::us
< 10) { // <10us
139 } else if (age
/ SimClock::Int::us
< 100) { // <100us
141 } else if (age
/ SimClock::Int::ms
< 1) { // <1ms
143 } else if (age
/ SimClock::Int::ms
< 10) { // <10ms
146 age_index
= 4; // >10ms
148 ageTaskId
[blk
.task_id
][age_index
]++;
153 BaseTags::computeStats()
155 for (unsigned i
= 0; i
< ContextSwitchTaskId::NumTaskId
; ++i
) {
156 occupanciesTaskId
[i
] = 0;
157 for (unsigned j
= 0; j
< 5; ++j
) {
162 forEachBlk([this](CacheBlk
&blk
) { computeStatsVisitor(blk
); });
170 auto print_blk
= [&str
](CacheBlk
&blk
) {
172 str
+= csprintf("\tset: %d way: %d %s\n", blk
.set
, blk
.way
,
175 forEachBlk(print_blk
);
178 str
= "no valid tags\n";
186 ClockedObject::regStats();
188 using namespace Stats
;
191 .name(name() + ".tagsinuse")
192 .desc("Cycle average of tags in use")
196 .name(name() + ".total_refs")
197 .desc("Total number of references to valid blocks.")
201 .name(name() + ".sampled_refs")
202 .desc("Sample count of references to valid blocks.")
206 .name(name() + ".avg_refs")
207 .desc("Average number of references to valid blocks.")
210 avgRefs
= totalRefs
/sampledRefs
;
213 .name(name() + ".warmup_cycle")
214 .desc("Cycle when the warmup percentage was hit.")
218 .init(cache
->system
->maxMasters())
219 .name(name() + ".occ_blocks")
220 .desc("Average occupied blocks per requestor")
221 .flags(nozero
| nonan
)
223 for (int i
= 0; i
< cache
->system
->maxMasters(); i
++) {
224 occupancies
.subname(i
, cache
->system
->getMasterName(i
));
228 .name(name() + ".occ_percent")
229 .desc("Average percentage of cache occupancy")
230 .flags(nozero
| total
)
232 for (int i
= 0; i
< cache
->system
->maxMasters(); i
++) {
233 avgOccs
.subname(i
, cache
->system
->getMasterName(i
));
236 avgOccs
= occupancies
/ Stats::constant(numBlocks
);
239 .init(ContextSwitchTaskId::NumTaskId
)
240 .name(name() + ".occ_task_id_blocks")
241 .desc("Occupied blocks per task id")
242 .flags(nozero
| nonan
)
246 .init(ContextSwitchTaskId::NumTaskId
, 5)
247 .name(name() + ".age_task_id_blocks")
248 .desc("Occupied blocks per task id")
249 .flags(nozero
| nonan
)
253 .name(name() + ".occ_task_id_percent")
254 .desc("Percentage of cache occupancy per task id")
258 percentOccsTaskId
= occupanciesTaskId
/ Stats::constant(numBlocks
);
261 .name(name() + ".tag_accesses")
262 .desc("Number of tag accesses")
266 .name(name() + ".data_accesses")
267 .desc("Number of data accesses")
270 registerDumpCallback(new BaseTagsDumpCallback(this));
271 registerExitCallback(new BaseTagsCallback(this));