Mem: Use cycles to express cache-related latencies
[gem5.git] / src / mem / cache / tags / cacheset.cc
1 /*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Lisa Hsu
29 */
30
31
32 #include "mem/cache/tags/cacheset.hh"
33
34 CacheBlk*
35 CacheSet::findBlk(Addr tag) const
36 {
37 for (int i = 0; i < assoc; ++i) {
38 if (blks[i]->tag == tag && blks[i]->isValid()) {
39 return blks[i];
40 }
41 }
42 return 0;
43 }
44
45 void
46 CacheSet::moveToHead(CacheBlk *blk)
47 {
48 // nothing to do if blk is already head
49 if (blks[0] == blk)
50 return;
51
52 // write 'next' block into blks[i], moving up from MRU toward LRU
53 // until we overwrite the block we moved to head.
54
55 // start by setting up to write 'blk' into blks[0]
56 int i = 0;
57 CacheBlk *next = blk;
58
59 do {
60 assert(i < assoc);
61 // swap blks[i] and next
62 CacheBlk *tmp = blks[i];
63 blks[i] = next;
64 next = tmp;
65 ++i;
66 } while (next != blk);
67 }
68
69 void
70 CacheSet::moveToTail(CacheBlk *blk)
71 {
72 // nothing to do if blk is already tail
73 if (blks[assoc-1] == blk)
74 return;
75
76 // write 'next' block into blks[i], moving from LRU to MRU
77 // until we overwrite the block we moved to tail.
78
79 // start by setting up to write 'blk' into tail
80 int i = assoc - 1;
81 CacheBlk *next = blk;
82
83 do {
84 assert(i >= 0);
85 // swap blks[i] and next
86 CacheBlk *tmp = blks[i];
87 blks[i] = next;
88 next = tmp;
89 --i;
90 } while (next != blk);
91 }
92