src/mem/cache/tags/fa_lru.cc

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  */
  42
  43 /**
  44  * @file
  45  * Definitions a fully associative LRU tagstore.
  46  */
  47
  48 #include "mem/cache/tags/fa_lru.hh"
  49
  50 #include <cassert>
  51 #include <sstream>
  52
  53 #include "base/intmath.hh"
  54 #include "base/misc.hh"
  55
  56 using namespace std;
  57
  58 FALRU::FALRU(const Params *p)
  59     : BaseTags(p), cacheBoundaries(nullptr)
  60 {
  61     if (!isPowerOf2(blkSize))
  62         fatal("cache block size (in bytes) `%d' must be a power of two",
  63               blkSize);
  64     if (!isPowerOf2(size))
  65         fatal("Cache Size must be power of 2 for now");
  66
  67     // Track all cache sizes from 128K up by powers of 2
  68     numCaches = floorLog2(size) - 17;
  69     if (numCaches >0){
  70         cacheBoundaries = new FALRUBlk *[numCaches];
  71         cacheMask = (ULL(1) << numCaches) - 1;
  72     } else {
  73         cacheMask = 0;
  74     }
  75
  76     warmupBound = size/blkSize;
  77     numBlocks = size/blkSize;
  78
  79     blks = new FALRUBlk[numBlocks];
  80     head = &(blks[0]);
  81     tail = &(blks[numBlocks-1]);
  82
  83     head->prev = nullptr;
  84     head->next = &(blks[1]);
  85     head->inCache = cacheMask;
  86
  87     tail->prev = &(blks[numBlocks-2]);
  88     tail->next = nullptr;
  89     tail->inCache = 0;
  90
  91     unsigned index = (1 << 17) / blkSize;
  92     unsigned j = 0;
  93     int flags = cacheMask;
  94     for (unsigned i = 1; i < numBlocks - 1; i++) {
  95         blks[i].inCache = flags;
  96         if (i == index - 1){
  97             cacheBoundaries[j] = &(blks[i]);
  98             flags &= ~ (1<<j);
  99             ++j;
 100             index = index << 1;
 101         }
 102         blks[i].prev = &(blks[i-1]);
 103         blks[i].next = &(blks[i+1]);
 104         blks[i].isTouched = false;
 105         blks[i].set = 0;
 106         blks[i].way = i;
 107     }
 108     assert(j == numCaches);
 109     assert(index == numBlocks);
 110     //assert(check());
 111 }
 112
 113 FALRU::~FALRU()
 114 {
 115     if (numCaches)
 116         delete[] cacheBoundaries;
 117
 118     delete[] blks;
 119 }
 120
 121 void
 122 FALRU::regStats()
 123 {
 124     using namespace Stats;
 125     BaseTags::regStats();
 126     hits
 127         .init(numCaches+1)
 128         .name(name() + ".falru_hits")
 129         .desc("The number of hits in each cache size.")
 130         ;
 131     misses
 132         .init(numCaches+1)
 133         .name(name() + ".falru_misses")
 134         .desc("The number of misses in each cache size.")
 135         ;
 136     accesses
 137         .name(name() + ".falru_accesses")
 138         .desc("The number of accesses to the FA LRU cache.")
 139         ;
 140
 141     for (unsigned i = 0; i <= numCaches; ++i) {
 142         stringstream size_str;
 143         if (i < 3){
 144             size_str << (1<<(i+7)) <<"K";
 145         } else {
 146             size_str << (1<<(i-3)) <<"M";
 147         }
 148
 149         hits.subname(i, size_str.str());
 150         hits.subdesc(i, "Hits in a " + size_str.str() +" cache");
 151         misses.subname(i, size_str.str());
 152         misses.subdesc(i, "Misses in a " + size_str.str() +" cache");
 153     }
 154 }
 155
 156 FALRUBlk *
 157 FALRU::hashLookup(Addr addr) const
 158 {
 159     tagIterator iter = tagHash.find(addr);
 160     if (iter != tagHash.end()) {
 161         return (*iter).second;
 162     }
 163     return nullptr;
 164 }
 165
 166 void
 167 FALRU::invalidate(CacheBlk *blk)
 168 {
 169     assert(blk);
 170     tagsInUse--;
 171 }
 172
 173 CacheBlk*
 174 FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src)
 175 {
 176     return accessBlock(addr, is_secure, lat, context_src, 0);
 177 }
 178
 179 CacheBlk*
 180 FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src,
 181                    int *inCache)
 182 {
 183     accesses++;
 184     int tmp_in_cache = 0;
 185     Addr blkAddr = blkAlign(addr);
 186     FALRUBlk* blk = hashLookup(blkAddr);
 187
 188     if (blk && blk->isValid()) {
 189         assert(blk->tag == blkAddr);
 190         tmp_in_cache = blk->inCache;
 191         for (unsigned i = 0; i < numCaches; i++) {
 192             if (1<<i & blk->inCache) {
 193                 hits[i]++;
 194             } else {
 195                 misses[i]++;
 196             }
 197         }
 198         hits[numCaches]++;
 199         if (blk != head){
 200             moveToHead(blk);
 201         }
 202     } else {
 203         blk = nullptr;
 204         for (unsigned i = 0; i <= numCaches; ++i) {
 205             misses[i]++;
 206         }
 207     }
 208     if (inCache) {
 209         *inCache = tmp_in_cache;
 210     }
 211
 212     lat = accessLatency;
 213     //assert(check());
 214     return blk;
 215 }
 216
 217
 218 CacheBlk*
 219 FALRU::findBlock(Addr addr, bool is_secure) const
 220 {
 221     Addr blkAddr = blkAlign(addr);
 222     FALRUBlk* blk = hashLookup(blkAddr);
 223
 224     if (blk && blk->isValid()) {
 225         assert(blk->tag == blkAddr);
 226     } else {
 227         blk = nullptr;
 228     }
 229     return blk;
 230 }
 231
 232 CacheBlk*
 233 FALRU::findBlockBySetAndWay(int set, int way) const
 234 {
 235     assert(set == 0);
 236     return &blks[way];
 237 }
 238
 239 CacheBlk*
 240 FALRU::findVictim(Addr addr)
 241 {
 242     FALRUBlk * blk = tail;
 243     assert(blk->inCache == 0);
 244     moveToHead(blk);
 245     tagHash.erase(blk->tag);
 246     tagHash[blkAlign(addr)] = blk;
 247     if (blk->isValid()) {
 248         replacements[0]++;
 249     } else {
 250         tagsInUse++;
 251         blk->isTouched = true;
 252         if (!warmedUp && tagsInUse.value() >= warmupBound) {
 253             warmedUp = true;
 254             warmupCycle = curTick();
 255         }
 256     }
 257     //assert(check());
 258     return blk;
 259 }
 260
 261 void
 262 FALRU::insertBlock(PacketPtr pkt, CacheBlk *blk)
 263 {
 264 }
 265
 266 void
 267 FALRU::moveToHead(FALRUBlk *blk)
 268 {
 269     int updateMask = blk->inCache ^ cacheMask;
 270     for (unsigned i = 0; i < numCaches; i++){
 271         if ((1<<i) & updateMask) {
 272             cacheBoundaries[i]->inCache &= ~(1<<i);
 273             cacheBoundaries[i] = cacheBoundaries[i]->prev;
 274         } else if (cacheBoundaries[i] == blk) {
 275             cacheBoundaries[i] = blk->prev;
 276         }
 277     }
 278     blk->inCache = cacheMask;
 279     if (blk != head) {
 280         if (blk == tail){
 281             assert(blk->next == nullptr);
 282             tail = blk->prev;
 283             tail->next = nullptr;
 284         } else {
 285             blk->prev->next = blk->next;
 286             blk->next->prev = blk->prev;
 287         }
 288         blk->next = head;
 289         blk->prev = nullptr;
 290         head->prev = blk;
 291         head = blk;
 292     }
 293 }
 294
 295 bool
 296 FALRU::check()
 297 {
 298     FALRUBlk* blk = head;
 299     int tot_size = 0;
 300     int boundary = 1<<17;
 301     int j = 0;
 302     int flags = cacheMask;
 303     while (blk) {
 304         tot_size += blkSize;
 305         if (blk->inCache != flags) {
 306             return false;
 307         }
 308         if (tot_size == boundary && blk != tail) {
 309             if (cacheBoundaries[j] != blk) {
 310                 return false;
 311             }
 312             flags &=~(1 << j);
 313             boundary = boundary<<1;
 314             ++j;
 315         }
 316         blk = blk->next;
 317     }
 318     return true;
 319 }
 320
 321 FALRU *
 322 FALRUParams::create()
 323 {
 324     return new FALRU(this);
 325 }
 326