src/mem/cache/tags/fa_lru.cc

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  */
  42
  43 /**
  44  * @file
  45  * Definitions a fully associative LRU tagstore.
  46  */
  47
  48 #include <cassert>
  49 #include <sstream>
  50
  51 #include "base/intmath.hh"
  52 #include "base/misc.hh"
  53 #include "mem/cache/tags/fa_lru.hh"
  54
  55 using namespace std;
  56
  57 FALRU::FALRU(const Params *p)
  58     : BaseTags(p)
  59 {
  60     if (!isPowerOf2(blkSize))
  61         fatal("cache block size (in bytes) `%d' must be a power of two",
  62               blkSize);
  63     if (!(hitLatency > 0))
  64         fatal("Access latency in cycles must be at least one cycle");
  65     if (!isPowerOf2(size))
  66         fatal("Cache Size must be power of 2 for now");
  67
  68     // Track all cache sizes from 128K up by powers of 2
  69     numCaches = floorLog2(size) - 17;
  70     if (numCaches >0){
  71         cacheBoundaries = new FALRUBlk *[numCaches];
  72         cacheMask = (1 << numCaches) - 1;
  73     } else {
  74         cacheMask = 0;
  75     }
  76
  77     warmedUp = false;
  78     warmupBound = size/blkSize;
  79     numBlocks = size/blkSize;
  80
  81     blks = new FALRUBlk[numBlocks];
  82     head = &(blks[0]);
  83     tail = &(blks[numBlocks-1]);
  84
  85     head->prev = NULL;
  86     head->next = &(blks[1]);
  87     head->inCache = cacheMask;
  88
  89     tail->prev = &(blks[numBlocks-2]);
  90     tail->next = NULL;
  91     tail->inCache = 0;
  92
  93     unsigned index = (1 << 17) / blkSize;
  94     unsigned j = 0;
  95     int flags = cacheMask;
  96     for (unsigned i = 1; i < numBlocks - 1; i++) {
  97         blks[i].inCache = flags;
  98         if (i == index - 1){
  99             cacheBoundaries[j] = &(blks[i]);
 100             flags &= ~ (1<<j);
 101             ++j;
 102             index = index << 1;
 103         }
 104         blks[i].prev = &(blks[i-1]);
 105         blks[i].next = &(blks[i+1]);
 106         blks[i].isTouched = false;
 107     }
 108     assert(j == numCaches);
 109     assert(index == numBlocks);
 110     //assert(check());
 111 }
 112
 113 FALRU::~FALRU()
 114 {
 115     if (numCaches)
 116         delete[] cacheBoundaries;
 117
 118     delete[] blks;
 119 }
 120
 121 void
 122 FALRU::regStats()
 123 {
 124     using namespace Stats;
 125     BaseTags::regStats();
 126     hits
 127         .init(numCaches+1)
 128         .name(name() + ".falru_hits")
 129         .desc("The number of hits in each cache size.")
 130         ;
 131     misses
 132         .init(numCaches+1)
 133         .name(name() + ".falru_misses")
 134         .desc("The number of misses in each cache size.")
 135         ;
 136     accesses
 137         .name(name() + ".falru_accesses")
 138         .desc("The number of accesses to the FA LRU cache.")
 139         ;
 140
 141     for (unsigned i = 0; i <= numCaches; ++i) {
 142         stringstream size_str;
 143         if (i < 3){
 144             size_str << (1<<(i+7)) <<"K";
 145         } else {
 146             size_str << (1<<(i-3)) <<"M";
 147         }
 148
 149         hits.subname(i, size_str.str());
 150         hits.subdesc(i, "Hits in a " + size_str.str() +" cache");
 151         misses.subname(i, size_str.str());
 152         misses.subdesc(i, "Misses in a " + size_str.str() +" cache");
 153     }
 154 }
 155
 156 FALRUBlk *
 157 FALRU::hashLookup(Addr addr) const
 158 {
 159     tagIterator iter = tagHash.find(addr);
 160     if (iter != tagHash.end()) {
 161         return (*iter).second;
 162     }
 163     return NULL;
 164 }
 165
 166 void
 167 FALRU::invalidate(FALRU::BlkType *blk)
 168 {
 169     assert(blk);
 170     tagsInUse--;
 171 }
 172
 173 FALRUBlk*
 174 FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src,
 175                    int *inCache)
 176 {
 177     accesses++;
 178     int tmp_in_cache = 0;
 179     Addr blkAddr = blkAlign(addr);
 180     FALRUBlk* blk = hashLookup(blkAddr);
 181
 182     if (blk && blk->isValid()) {
 183         assert(blk->tag == blkAddr);
 184         tmp_in_cache = blk->inCache;
 185         for (unsigned i = 0; i < numCaches; i++) {
 186             if (1<<i & blk->inCache) {
 187                 hits[i]++;
 188             } else {
 189                 misses[i]++;
 190             }
 191         }
 192         hits[numCaches]++;
 193         if (blk != head){
 194             moveToHead(blk);
 195         }
 196     } else {
 197         blk = NULL;
 198         for (unsigned i = 0; i <= numCaches; ++i) {
 199             misses[i]++;
 200         }
 201     }
 202     if (inCache) {
 203         *inCache = tmp_in_cache;
 204     }
 205
 206     lat = hitLatency;
 207     //assert(check());
 208     return blk;
 209 }
 210
 211
 212 FALRUBlk*
 213 FALRU::findBlock(Addr addr, bool is_secure) const
 214 {
 215     Addr blkAddr = blkAlign(addr);
 216     FALRUBlk* blk = hashLookup(blkAddr);
 217
 218     if (blk && blk->isValid()) {
 219         assert(blk->tag == blkAddr);
 220     } else {
 221         blk = NULL;
 222     }
 223     return blk;
 224 }
 225
 226 FALRUBlk*
 227 FALRU::findVictim(Addr addr, PacketList &writebacks)
 228 {
 229     FALRUBlk * blk = tail;
 230     assert(blk->inCache == 0);
 231     moveToHead(blk);
 232     tagHash.erase(blk->tag);
 233     tagHash[blkAlign(addr)] = blk;
 234     if (blk->isValid()) {
 235         replacements[0]++;
 236     } else {
 237         tagsInUse++;
 238         blk->isTouched = true;
 239         if (!warmedUp && tagsInUse.value() >= warmupBound) {
 240             warmedUp = true;
 241             warmupCycle = curTick();
 242         }
 243     }
 244     //assert(check());
 245     return blk;
 246 }
 247
 248 void
 249 FALRU::insertBlock(PacketPtr pkt, FALRU::BlkType *blk)
 250 {
 251 }
 252
 253 void
 254 FALRU::moveToHead(FALRUBlk *blk)
 255 {
 256     int updateMask = blk->inCache ^ cacheMask;
 257     for (unsigned i = 0; i < numCaches; i++){
 258         if ((1<<i) & updateMask) {
 259             cacheBoundaries[i]->inCache &= ~(1<<i);
 260             cacheBoundaries[i] = cacheBoundaries[i]->prev;
 261         } else if (cacheBoundaries[i] == blk) {
 262             cacheBoundaries[i] = blk->prev;
 263         }
 264     }
 265     blk->inCache = cacheMask;
 266     if (blk != head) {
 267         if (blk == tail){
 268             assert(blk->next == NULL);
 269             tail = blk->prev;
 270             tail->next = NULL;
 271         } else {
 272             blk->prev->next = blk->next;
 273             blk->next->prev = blk->prev;
 274         }
 275         blk->next = head;
 276         blk->prev = NULL;
 277         head->prev = blk;
 278         head = blk;
 279     }
 280 }
 281
 282 bool
 283 FALRU::check()
 284 {
 285     FALRUBlk* blk = head;
 286     int tot_size = 0;
 287     int boundary = 1<<17;
 288     int j = 0;
 289     int flags = cacheMask;
 290     while (blk) {
 291         tot_size += blkSize;
 292         if (blk->inCache != flags) {
 293             return false;
 294         }
 295         if (tot_size == boundary && blk != tail) {
 296             if (cacheBoundaries[j] != blk) {
 297                 return false;
 298             }
 299             flags &=~(1 << j);
 300             boundary = boundary<<1;
 301             ++j;
 302         }
 303         blk = blk->next;
 304     }
 305     return true;
 306 }
 307
 308 void
 309 FALRU::clearLocks()
 310 {
 311     for (int i = 0; i < numBlocks; i++){
 312         blks[i].clearLoadLocks();
 313     }
 314 }
 315
 316 FALRU *
 317 FALRUParams::create()
 318 {
 319     return new FALRU(this);
 320 }
 321