src/mem/cache/tags/fa_lru.hh

   1 /*
   2  * Copyright (c) 2012-2013,2016,2018 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
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   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
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  20  * notice, this list of conditions and the following disclaimer;
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  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Erik Hallnor
  41  *          Nikos Nikoleris
  42  */
  43
  44 /**
  45  * @file
  46  * Declaration of a fully associative LRU tag store.
  47  */
  48
  49 #ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
  50 #define __MEM_CACHE_TAGS_FA_LRU_HH__
  51
  52 #include <cstdint>
  53 #include <functional>
  54 #include <string>
  55 #include <unordered_map>
  56
  57 #include "base/bitfield.hh"
  58 #include "base/intmath.hh"
  59 #include "base/logging.hh"
  60 #include "base/statistics.hh"
  61 #include "base/types.hh"
  62 #include "mem/cache/blk.hh"
  63 #include "mem/cache/tags/base.hh"
  64 #include "mem/packet.hh"
  65 #include "params/FALRU.hh"
  66
  67 // Uncomment to enable sanity checks for the FALRU cache and the
  68 // TrackedCaches class
  69 //#define FALRU_DEBUG
  70
  71 // A bitmask of the caches we are keeping track of. Currently the
  72 // lowest bit is the smallest cache we are tracking, as it is
  73 // specified by the corresponding parameter. The rest of the bits are
  74 // for exponentially growing cache sizes.
  75 typedef uint32_t CachesMask;
  76
  77 /**
  78  * A fully associative cache block.
  79  */
  80 class FALRUBlk : public CacheBlk
  81 {
  82   public:
  83     /** The previous block in LRU order. */
  84     FALRUBlk *prev;
  85     /** The next block in LRU order. */
  86     FALRUBlk *next;
  87
  88     /** A bit mask of the caches that fit this block. */
  89     CachesMask inCachesMask;
  90 };
  91
  92 /**
  93  * A fully associative LRU cache. Keeps statistics for accesses to a number of
  94  * cache sizes at once.
  95  */
  96 class FALRU : public BaseTags
  97 {
  98   public:
  99     /** Typedef the block type used in this class. */
 100     typedef FALRUBlk BlkType;
 101
 102   protected:
 103     /** The cache blocks. */
 104     FALRUBlk *blks;
 105
 106     /** The MRU block. */
 107     FALRUBlk *head;
 108     /** The LRU block. */
 109     FALRUBlk *tail;
 110
 111     /** Hash table type mapping addresses to cache block pointers. */
 112     typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t;
 113     /** Iterator into the address hash table. */
 114     typedef hash_t::const_iterator tagIterator;
 115
 116     /** The address hash table. */
 117     hash_t tagHash;
 118
 119     /**
 120      * Find the cache block for the given address.
 121      * @param addr The address to find.
 122      * @return The cache block of the address, if any.
 123      */
 124     FALRUBlk * hashLookup(Addr addr) const;
 125
 126     /**
 127      * Move a cache block to the MRU position.
 128      *
 129      * @param blk The block to promote.
 130      */
 131     void moveToHead(FALRUBlk *blk);
 132
 133     /**
 134      * Move a cache block to the LRU position.
 135      *
 136      * @param blk The block to demote.
 137      */
 138     void moveToTail(FALRUBlk *blk);
 139
 140   public:
 141     typedef FALRUParams Params;
 142
 143     /**
 144      * Construct and initialize this cache tagstore.
 145      */
 146     FALRU(const Params *p);
 147     ~FALRU();
 148
 149     /**
 150      * Register the stats for this object.
 151      */
 152     void regStats() override;
 153
 154     /**
 155      * Invalidate a cache block.
 156      * @param blk The block to invalidate.
 157      */
 158     void invalidate(CacheBlk *blk) override;
 159
 160     /**
 161      * Access block and update replacement data.  May not succeed, in which
 162      * case nullptr pointer is returned.  This has all the implications of a
 163      * cache access and should only be used as such.
 164      * Returns the access latency and inCachesMask flags as a side effect.
 165      * @param addr The address to look for.
 166      * @param is_secure True if the target memory space is secure.
 167      * @param lat The latency of the access.
 168      * @param in_cache_mask Mask indicating the caches in which the blk fits.
 169      * @return Pointer to the cache block.
 170      */
 171     CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
 172                           CachesMask *in_cache_mask);
 173
 174     /**
 175      * Just a wrapper of above function to conform with the base interface.
 176      */
 177     CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override;
 178
 179     /**
 180      * Find the block in the cache, do not update the replacement data.
 181      * @param addr The address to look for.
 182      * @param is_secure True if the target memory space is secure.
 183      * @param asid The address space ID.
 184      * @return Pointer to the cache block.
 185      */
 186     CacheBlk* findBlock(Addr addr, bool is_secure) const override;
 187
 188     /**
 189      * Find replacement victim based on address.
 190      *
 191      * @param addr Address to find a victim for.
 192      * @return Cache block to be replaced.
 193      */
 194     CacheBlk* findVictim(Addr addr) override;
 195
 196     /**
 197      * Insert the new block into the cache and update replacement data.
 198      *
 199      * @param pkt Packet holding the address to update
 200      * @param blk The block to update.
 201      */
 202     void insertBlock(PacketPtr pkt, CacheBlk *blk) override;
 203
 204     /**
 205      * Find the cache block given set and way
 206      * @param set The set of the block.
 207      * @param way The way of the block.
 208      * @return The cache block.
 209      */
 210     CacheBlk* findBlockBySetAndWay(int set, int way) const override;
 211
 212     /**
 213      * Generate the tag from the addres. For fully associative this is just the
 214      * block address.
 215      * @param addr The address to get the tag from.
 216      * @return The tag.
 217      */
 218     Addr extractTag(Addr addr) const override
 219     {
 220         return blkAlign(addr);
 221     }
 222
 223     /**
 224      * Regenerate the block address from the tag.
 225      *
 226      * @param block The block.
 227      * @return the block address.
 228      */
 229     Addr regenerateBlkAddr(const CacheBlk* blk) const override
 230     {
 231         return blk->tag;
 232     }
 233
 234     void forEachBlk(std::function<void(CacheBlk &)> visitor) override {
 235         for (int i = 0; i < numBlocks; i++) {
 236             visitor(blks[i]);
 237         }
 238     }
 239
 240     bool anyBlk(std::function<bool(CacheBlk &)> visitor) override {
 241         for (int i = 0; i < numBlocks; i++) {
 242             if (visitor(blks[i])) {
 243                 return true;
 244             }
 245         }
 246         return false;
 247     }
 248
 249   private:
 250     /**
 251      * Mechanism that allows us to simultaneously collect miss
 252      * statistics for multiple caches. Currently, we keep track of
 253      * caches from a set minimum size of interest up to the actual
 254      * cache size.
 255      */
 256     class CacheTracking
 257     {
 258       public:
 259         CacheTracking(unsigned min_size, unsigned max_size,
 260                       unsigned block_size)
 261             : blkSize(block_size),
 262               minTrackedSize(min_size),
 263               numTrackedCaches(max_size > min_size ?
 264                                floorLog2(max_size) - floorLog2(min_size) : 0),
 265               inAllCachesMask(mask(numTrackedCaches)),
 266               boundaries(new FALRUBlk *[numTrackedCaches])
 267         {
 268             fatal_if(numTrackedCaches > sizeof(CachesMask) * 8,
 269                      "Not enough bits (%s) in type CachesMask type to keep "
 270                      "track of %d caches\n", sizeof(CachesMask),
 271                      numTrackedCaches);
 272         }
 273
 274         ~CacheTracking()
 275         {
 276             delete[] boundaries;
 277         }
 278
 279         /**
 280          * Initialiaze cache blocks and the tracking mechanism
 281          *
 282          * All blocks in the cache need to be initialized once.
 283          *
 284          * @param blk the MRU block
 285          * @param blk the LRU block
 286          */
 287         void init(FALRUBlk *head, FALRUBlk *tail);
 288
 289         /**
 290          * Update boundaries as a block will be moved to the MRU.
 291          *
 292          * For all caches that didn't fit the block before moving it,
 293          * we move their boundaries one block closer to the MRU. We
 294          * also update InCacheMasks as neccessary.
 295          *
 296          * @param blk the block that will be moved to the head
 297          */
 298         void moveBlockToHead(FALRUBlk *blk);
 299
 300         /**
 301          * Update boundaries as a block will be moved to the LRU.
 302          *
 303          * For all caches that fitted the block before moving it, we
 304          * move their boundaries one block closer to the LRU. We
 305          * also update InCacheMasks as neccessary.
 306          *
 307          * @param blk the block that will be moved to the head
 308          */
 309         void moveBlockToTail(FALRUBlk *blk);
 310
 311         /**
 312          * Notify of a block access.
 313          *
 314          * This should be called every time a block is accessed and it
 315          * updates statistics. If the input block is nullptr then we
 316          * treat the access as a miss. The block's InCacheMask
 317          * determines the caches in which the block fits.
 318          *
 319          * @param blk the block to record the access for
 320          */
 321         void recordAccess(FALRUBlk *blk);
 322
 323         /**
 324          * Check that the tracking mechanism is in consistent state.
 325          *
 326          * Iterate from the head (MRU) to the tail (LRU) of the list
 327          * of blocks and assert the inCachesMask and the boundaries
 328          * are in consistent state.
 329          *
 330          * @param head the MRU block of the actual cache
 331          * @param head the LRU block of the actual cache
 332          */
 333         void check(FALRUBlk *head, FALRUBlk *tail);
 334
 335         /**
 336          * Register the stats for this object.
 337          */
 338         void regStats(std::string name);
 339
 340       private:
 341         /** The size of the cache block */
 342         const unsigned blkSize;
 343         /** The smallest cache we are tracking */
 344         const unsigned minTrackedSize;
 345         /** The number of different size caches being tracked. */
 346         const int numTrackedCaches;
 347         /** A mask for all cache being tracked. */
 348         const CachesMask inAllCachesMask;
 349         /** Array of pointers to blocks at the cache boundaries. */
 350         FALRUBlk** boundaries;
 351
 352       protected:
 353         /**
 354          * @defgroup FALRUStats Fully Associative LRU specific statistics
 355          * The FA lru stack lets us track multiple cache sizes at once. These
 356          * statistics track the hits and misses for different cache sizes.
 357          * @{
 358          */
 359
 360         /** Hits in each cache */
 361         Stats::Vector hits;
 362         /** Misses in each cache */
 363         Stats::Vector misses;
 364         /** Total number of accesses */
 365         Stats::Scalar accesses;
 366
 367         /**
 368          * @}
 369          */
 370     };
 371     CacheTracking cacheTracking;
 372 };
 373
 374 #endif // __MEM_CACHE_TAGS_FA_LRU_HH__