Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
[gem5.git] / src / mem / cache / tags / lru.hh
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31 /**
32 * @file
33 * Declaration of a LRU tag store.
34 */
35
36 #ifndef __LRU_HH__
37 #define __LRU_HH__
38
39 #include <cstring>
40 #include <list>
41
42 #include "mem/cache/cache_blk.hh" // base class
43 #include "mem/packet.hh" // for inlined functions
44 #include <assert.h>
45 #include "mem/cache/tags/base_tags.hh"
46
47 class BaseCache;
48
49 /**
50 * LRU cache block.
51 */
52 class LRUBlk : public CacheBlk {
53 public:
54 /** Has this block been touched? Used to aid calculation of warmup time. */
55 bool isTouched;
56 };
57
58 /**
59 * An associative set of cache blocks.
60 */
61 class CacheSet
62 {
63 public:
64 /** The associativity of this set. */
65 int assoc;
66
67 /** Cache blocks in this set, maintained in LRU order 0 = MRU. */
68 LRUBlk **blks;
69
70 /**
71 * Find a block matching the tag in this set.
72 * @param asid The address space ID.
73 * @param tag The Tag to find.
74 * @return Pointer to the block if found.
75 */
76 LRUBlk* findBlk(Addr tag) const;
77
78 /**
79 * Move the given block to the head of the list.
80 * @param blk The block to move.
81 */
82 void moveToHead(LRUBlk *blk);
83 };
84
85 /**
86 * A LRU cache tag store.
87 */
88 class LRU : public BaseTags
89 {
90 public:
91 /** Typedef the block type used in this tag store. */
92 typedef LRUBlk BlkType;
93 /** Typedef for a list of pointers to the local block class. */
94 typedef std::list<LRUBlk*> BlkList;
95 protected:
96 /** The number of sets in the cache. */
97 const int numSets;
98 /** The number of bytes in a block. */
99 const int blkSize;
100 /** The associativity of the cache. */
101 const int assoc;
102 /** The hit latency. */
103 const int hitLatency;
104
105 /** The cache sets. */
106 CacheSet *sets;
107
108 /** The cache blocks. */
109 LRUBlk *blks;
110 /** The data blocks, 1 per cache block. */
111 uint8_t *dataBlks;
112
113 /** The amount to shift the address to get the set. */
114 int setShift;
115 /** The amount to shift the address to get the tag. */
116 int tagShift;
117 /** Mask out all bits that aren't part of the set index. */
118 unsigned setMask;
119 /** Mask out all bits that aren't part of the block offset. */
120 unsigned blkMask;
121
122 public:
123 /**
124 * Construct and initialize this tag store.
125 * @param _numSets The number of sets in the cache.
126 * @param _blkSize The number of bytes in a block.
127 * @param _assoc The associativity of the cache.
128 * @param _hit_latency The latency in cycles for a hit.
129 */
130 LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency);
131
132 /**
133 * Destructor
134 */
135 virtual ~LRU();
136
137 /**
138 * Return the block size.
139 * @return the block size.
140 */
141 int getBlockSize()
142 {
143 return blkSize;
144 }
145
146 /**
147 * Return the subblock size. In the case of LRU it is always the block
148 * size.
149 * @return The block size.
150 */
151 int getSubBlockSize()
152 {
153 return blkSize;
154 }
155
156 /**
157 * Search for the address in the cache.
158 * @param asid The address space ID.
159 * @param addr The address to find.
160 * @return True if the address is in the cache.
161 */
162 bool probe(Addr addr) const;
163
164 /**
165 * Invalidate the given block.
166 * @param blk The block to invalidate.
167 */
168 void invalidateBlk(BlkType *blk);
169
170 /**
171 * Finds the given address in the cache and update replacement data.
172 * Returns the access latency as a side effect.
173 * @param addr The address to find.
174 * @param asid The address space ID.
175 * @param lat The access latency.
176 * @return Pointer to the cache block if found.
177 */
178 LRUBlk* findBlock(Addr addr, int &lat);
179
180 /**
181 * Finds the given address in the cache, do not update replacement data.
182 * @param addr The address to find.
183 * @param asid The address space ID.
184 * @return Pointer to the cache block if found.
185 */
186 LRUBlk* findBlock(Addr addr) const;
187
188 /**
189 * Find a replacement block for the address provided.
190 * @param pkt The request to a find a replacement candidate for.
191 * @param writebacks List for any writebacks to be performed.
192 * @param compress_blocks List of blocks to compress, for adaptive comp.
193 * @return The block to place the replacement in.
194 */
195 LRUBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
196 BlkList &compress_blocks);
197
198 /**
199 * Generate the tag from the given address.
200 * @param addr The address to get the tag from.
201 * @return The tag of the address.
202 */
203 Addr extractTag(Addr addr) const
204 {
205 return (addr >> tagShift);
206 }
207
208 /**
209 * Generate the tag from the given address.
210 * @param addr The address to get the tag from.
211 * @param blk Ignored.
212 * @return The tag of the address.
213 */
214 Addr extractTag(Addr addr, LRUBlk *blk) const
215 {
216 return (addr >> tagShift);
217 }
218
219 /**
220 * Calculate the set index from the address.
221 * @param addr The address to get the set from.
222 * @return The set index of the address.
223 */
224 int extractSet(Addr addr) const
225 {
226 return ((addr >> setShift) & setMask);
227 }
228
229 /**
230 * Get the block offset from an address.
231 * @param addr The address to get the offset of.
232 * @return The block offset.
233 */
234 int extractBlkOffset(Addr addr) const
235 {
236 return (addr & blkMask);
237 }
238
239 /**
240 * Align an address to the block size.
241 * @param addr the address to align.
242 * @return The block address.
243 */
244 Addr blkAlign(Addr addr) const
245 {
246 return (addr & ~(Addr)blkMask);
247 }
248
249 /**
250 * Regenerate the block address from the tag.
251 * @param tag The tag of the block.
252 * @param set The set of the block.
253 * @return The block address.
254 */
255 Addr regenerateBlkAddr(Addr tag, unsigned set) const
256 {
257 return ((tag << tagShift) | ((Addr)set << setShift));
258 }
259
260 /**
261 * Return the hit latency.
262 * @return the hit latency.
263 */
264 int getHitLatency() const
265 {
266 return hitLatency;
267 }
268
269 /**
270 * Read the data out of the internal storage of the given cache block.
271 * @param blk The cache block to read.
272 * @param data The buffer to read the data into.
273 * @return The cache block's data.
274 */
275 void readData(LRUBlk *blk, uint8_t *data)
276 {
277 std::memcpy(data, blk->data, blk->size);
278 }
279
280 /**
281 * Write data into the internal storage of the given cache block. Since in
282 * LRU does not store data differently this just needs to update the size.
283 * @param blk The cache block to write.
284 * @param data The data to write.
285 * @param size The number of bytes to write.
286 * @param writebacks A list for any writebacks to be performed. May be
287 * needed when writing to a compressed block.
288 */
289 void writeData(LRUBlk *blk, uint8_t *data, int size,
290 PacketList & writebacks)
291 {
292 assert(size <= blkSize);
293 blk->size = size;
294 }
295
296 /**
297 * Called at end of simulation to complete average block reference stats.
298 */
299 virtual void cleanupRefs();
300 };
301
302 #endif