SCons: Support building without an ISA
[gem5.git] / src / mem / cache / tags / lru.hh
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31 /**
32 * @file
33 * Declaration of a LRU tag store.
34 */
35
36 #ifndef __MEM_CACHE_TAGS_LRU_HH__
37 #define __MEM_CACHE_TAGS_LRU_HH__
38
39 #include <cassert>
40 #include <cstring>
41 #include <list>
42
43 #include "mem/cache/blk.hh"
44 #include "mem/cache/tags/base.hh"
45 #include "mem/packet.hh"
46
47 class BaseCache;
48 class CacheSet;
49
50
51 /**
52 * A LRU cache tag store.
53 */
54 class LRU : public BaseTags
55 {
56 public:
57 /** Typedef the block type used in this tag store. */
58 typedef CacheBlk BlkType;
59 /** Typedef for a list of pointers to the local block class. */
60 typedef std::list<BlkType*> BlkList;
61
62 protected:
63 /** The number of sets in the cache. */
64 const unsigned numSets;
65 /** The number of bytes in a block. */
66 const unsigned blkSize;
67 /** The associativity of the cache. */
68 const unsigned assoc;
69 /** The hit latency. */
70 const unsigned hitLatency;
71
72 /** The cache sets. */
73 CacheSet *sets;
74
75 /** The cache blocks. */
76 BlkType *blks;
77 /** The data blocks, 1 per cache block. */
78 uint8_t *dataBlks;
79
80 /** The amount to shift the address to get the set. */
81 int setShift;
82 /** The amount to shift the address to get the tag. */
83 int tagShift;
84 /** Mask out all bits that aren't part of the set index. */
85 unsigned setMask;
86 /** Mask out all bits that aren't part of the block offset. */
87 unsigned blkMask;
88
89 public:
90 /**
91 * Construct and initialize this tag store.
92 * @param _numSets The number of sets in the cache.
93 * @param _blkSize The number of bytes in a block.
94 * @param _assoc The associativity of the cache.
95 * @param _hit_latency The latency in cycles for a hit.
96 */
97 LRU(unsigned _numSets, unsigned _blkSize, unsigned _assoc,
98 unsigned _hit_latency);
99
100 /**
101 * Destructor
102 */
103 virtual ~LRU();
104
105 /**
106 * Return the block size.
107 * @return the block size.
108 */
109 unsigned
110 getBlockSize() const
111 {
112 return blkSize;
113 }
114
115 /**
116 * Return the subblock size. In the case of LRU it is always the block
117 * size.
118 * @return The block size.
119 */
120 unsigned
121 getSubBlockSize() const
122 {
123 return blkSize;
124 }
125
126 /**
127 * Invalidate the given block.
128 * @param blk The block to invalidate.
129 */
130 void invalidateBlk(BlkType *blk);
131
132 /**
133 * Access block and update replacement data. May not succeed, in which case
134 * NULL pointer is returned. This has all the implications of a cache
135 * access and should only be used as such. Returns the access latency as a side effect.
136 * @param addr The address to find.
137 * @param asid The address space ID.
138 * @param lat The access latency.
139 * @return Pointer to the cache block if found.
140 */
141 BlkType* accessBlock(Addr addr, int &lat, int context_src);
142
143 /**
144 * Finds the given address in the cache, do not update replacement data.
145 * i.e. This is a no-side-effect find of a block.
146 * @param addr The address to find.
147 * @param asid The address space ID.
148 * @return Pointer to the cache block if found.
149 */
150 BlkType* findBlock(Addr addr) const;
151
152 /**
153 * Find a block to evict for the address provided.
154 * @param addr The addr to a find a replacement candidate for.
155 * @param writebacks List for any writebacks to be performed.
156 * @return The candidate block.
157 */
158 BlkType* findVictim(Addr addr, PacketList &writebacks);
159
160 /**
161 * Insert the new block into the cache. For LRU this means inserting into
162 * the MRU position of the set.
163 * @param addr The address to update.
164 * @param blk The block to update.
165 */
166 void insertBlock(Addr addr, BlkType *blk, int context_src);
167
168 /**
169 * Generate the tag from the given address.
170 * @param addr The address to get the tag from.
171 * @return The tag of the address.
172 */
173 Addr extractTag(Addr addr) const
174 {
175 return (addr >> tagShift);
176 }
177
178 /**
179 * Calculate the set index from the address.
180 * @param addr The address to get the set from.
181 * @return The set index of the address.
182 */
183 int extractSet(Addr addr) const
184 {
185 return ((addr >> setShift) & setMask);
186 }
187
188 /**
189 * Get the block offset from an address.
190 * @param addr The address to get the offset of.
191 * @return The block offset.
192 */
193 int extractBlkOffset(Addr addr) const
194 {
195 return (addr & blkMask);
196 }
197
198 /**
199 * Align an address to the block size.
200 * @param addr the address to align.
201 * @return The block address.
202 */
203 Addr blkAlign(Addr addr) const
204 {
205 return (addr & ~(Addr)blkMask);
206 }
207
208 /**
209 * Regenerate the block address from the tag.
210 * @param tag The tag of the block.
211 * @param set The set of the block.
212 * @return The block address.
213 */
214 Addr regenerateBlkAddr(Addr tag, unsigned set) const
215 {
216 return ((tag << tagShift) | ((Addr)set << setShift));
217 }
218
219 /**
220 * Return the hit latency.
221 * @return the hit latency.
222 */
223 int getHitLatency() const
224 {
225 return hitLatency;
226 }
227 /**
228 *iterated through all blocks and clear all locks
229 *Needed to clear all lock tracking at once
230 */
231 virtual void clearLocks();
232
233 /**
234 * Called at end of simulation to complete average block reference stats.
235 */
236 virtual void cleanupRefs();
237 };
238
239 #endif // __MEM_CACHE_TAGS_LRU_HH__