Streamline Cache/Tags interface: get rid of redundant functions,
[gem5.git] / src / mem / cache / tags / lru.hh
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 */
30
31 /**
32 * @file
33 * Declaration of a LRU tag store.
34 */
35
36 #ifndef __LRU_HH__
37 #define __LRU_HH__
38
39 #include <list>
40
41 #include "mem/cache/cache_blk.hh" // base class
42 #include "mem/packet.hh" // for inlined functions
43 #include <assert.h>
44 #include "mem/cache/tags/base_tags.hh"
45
46 class BaseCache;
47
48 /**
49 * LRU cache block.
50 */
51 class LRUBlk : public CacheBlk {
52 public:
53 /** Has this block been touched? Used to aid calculation of warmup time. */
54 bool isTouched;
55 };
56
57 /**
58 * An associative set of cache blocks.
59 */
60 class CacheSet
61 {
62 public:
63 /** The associativity of this set. */
64 int assoc;
65
66 /** Cache blocks in this set, maintained in LRU order 0 = MRU. */
67 LRUBlk **blks;
68
69 /**
70 * Find a block matching the tag in this set.
71 * @param asid The address space ID.
72 * @param tag The Tag to find.
73 * @return Pointer to the block if found.
74 */
75 LRUBlk* findBlk(Addr tag) const;
76
77 /**
78 * Move the given block to the head of the list.
79 * @param blk The block to move.
80 */
81 void moveToHead(LRUBlk *blk);
82 };
83
84 /**
85 * A LRU cache tag store.
86 */
87 class LRU : public BaseTags
88 {
89 public:
90 /** Typedef the block type used in this tag store. */
91 typedef LRUBlk BlkType;
92 /** Typedef for a list of pointers to the local block class. */
93 typedef std::list<LRUBlk*> BlkList;
94 protected:
95 /** The number of sets in the cache. */
96 const int numSets;
97 /** The number of bytes in a block. */
98 const int blkSize;
99 /** The associativity of the cache. */
100 const int assoc;
101 /** The hit latency. */
102 const int hitLatency;
103
104 /** The cache sets. */
105 CacheSet *sets;
106
107 /** The cache blocks. */
108 LRUBlk *blks;
109 /** The data blocks, 1 per cache block. */
110 uint8_t *dataBlks;
111
112 /** The amount to shift the address to get the set. */
113 int setShift;
114 /** The amount to shift the address to get the tag. */
115 int tagShift;
116 /** Mask out all bits that aren't part of the set index. */
117 unsigned setMask;
118 /** Mask out all bits that aren't part of the block offset. */
119 unsigned blkMask;
120
121 public:
122 /**
123 * Construct and initialize this tag store.
124 * @param _numSets The number of sets in the cache.
125 * @param _blkSize The number of bytes in a block.
126 * @param _assoc The associativity of the cache.
127 * @param _hit_latency The latency in cycles for a hit.
128 */
129 LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency);
130
131 /**
132 * Destructor
133 */
134 virtual ~LRU();
135
136 /**
137 * Return the block size.
138 * @return the block size.
139 */
140 int getBlockSize()
141 {
142 return blkSize;
143 }
144
145 /**
146 * Return the subblock size. In the case of LRU it is always the block
147 * size.
148 * @return The block size.
149 */
150 int getSubBlockSize()
151 {
152 return blkSize;
153 }
154
155 /**
156 * Search for the address in the cache.
157 * @param asid The address space ID.
158 * @param addr The address to find.
159 * @return True if the address is in the cache.
160 */
161 bool probe(Addr addr) const;
162
163 /**
164 * Invalidate the given block.
165 * @param blk The block to invalidate.
166 */
167 void invalidateBlk(BlkType *blk);
168
169 /**
170 * Finds the given address in the cache and update replacement data.
171 * Returns the access latency as a side effect.
172 * @param addr The address to find.
173 * @param asid The address space ID.
174 * @param lat The access latency.
175 * @return Pointer to the cache block if found.
176 */
177 LRUBlk* findBlock(Addr addr, int &lat);
178
179 /**
180 * Finds the given address in the cache, do not update replacement data.
181 * @param addr The address to find.
182 * @param asid The address space ID.
183 * @return Pointer to the cache block if found.
184 */
185 LRUBlk* findBlock(Addr addr) const;
186
187 /**
188 * Find a replacement block for the address provided.
189 * @param pkt The request to a find a replacement candidate for.
190 * @param writebacks List for any writebacks to be performed.
191 * @param compress_blocks List of blocks to compress, for adaptive comp.
192 * @return The block to place the replacement in.
193 */
194 LRUBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks,
195 BlkList &compress_blocks);
196
197 /**
198 * Generate the tag from the given address.
199 * @param addr The address to get the tag from.
200 * @return The tag of the address.
201 */
202 Addr extractTag(Addr addr) const
203 {
204 return (addr >> tagShift);
205 }
206
207 /**
208 * Generate the tag from the given address.
209 * @param addr The address to get the tag from.
210 * @param blk Ignored.
211 * @return The tag of the address.
212 */
213 Addr extractTag(Addr addr, LRUBlk *blk) const
214 {
215 return (addr >> tagShift);
216 }
217
218 /**
219 * Calculate the set index from the address.
220 * @param addr The address to get the set from.
221 * @return The set index of the address.
222 */
223 int extractSet(Addr addr) const
224 {
225 return ((addr >> setShift) & setMask);
226 }
227
228 /**
229 * Get the block offset from an address.
230 * @param addr The address to get the offset of.
231 * @return The block offset.
232 */
233 int extractBlkOffset(Addr addr) const
234 {
235 return (addr & blkMask);
236 }
237
238 /**
239 * Align an address to the block size.
240 * @param addr the address to align.
241 * @return The block address.
242 */
243 Addr blkAlign(Addr addr) const
244 {
245 return (addr & ~(Addr)blkMask);
246 }
247
248 /**
249 * Regenerate the block address from the tag.
250 * @param tag The tag of the block.
251 * @param set The set of the block.
252 * @return The block address.
253 */
254 Addr regenerateBlkAddr(Addr tag, unsigned set) const
255 {
256 return ((tag << tagShift) | ((Addr)set << setShift));
257 }
258
259 /**
260 * Return the hit latency.
261 * @return the hit latency.
262 */
263 int getHitLatency() const
264 {
265 return hitLatency;
266 }
267
268 /**
269 * Read the data out of the internal storage of the given cache block.
270 * @param blk The cache block to read.
271 * @param data The buffer to read the data into.
272 * @return The cache block's data.
273 */
274 void readData(LRUBlk *blk, uint8_t *data)
275 {
276 memcpy(data, blk->data, blk->size);
277 }
278
279 /**
280 * Write data into the internal storage of the given cache block. Since in
281 * LRU does not store data differently this just needs to update the size.
282 * @param blk The cache block to write.
283 * @param data The data to write.
284 * @param size The number of bytes to write.
285 * @param writebacks A list for any writebacks to be performed. May be
286 * needed when writing to a compressed block.
287 */
288 void writeData(LRUBlk *blk, uint8_t *data, int size,
289 PacketList & writebacks)
290 {
291 assert(size <= blkSize);
292 blk->size = size;
293 }
294
295 /**
296 * Called at end of simulation to complete average block reference stats.
297 */
298 virtual void cleanupRefs();
299 };
300
301 #endif