Fix problems with unCacheable addresses in timing-coherence
[gem5.git] / src / mem / cache / tags / split_lru.cc
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Lisa Hsu
29 */
30
31 /**
32 * @file
33 * Definitions of LRU tag store for a partitioned cache.
34 */
35
36 #include <string>
37
38 #include "mem/cache/base_cache.hh"
39 #include "base/intmath.hh"
40 #include "mem/cache/tags/split_lru.hh"
41 #include "sim/root.hh"
42
43 using namespace std;
44
45 SplitBlk*
46 SplitCacheSet::findBlk(Addr tag) const
47 {
48 for (int i = 0; i < assoc; ++i) {
49 if (blks[i]->tag == tag && blks[i]->isValid()) {
50 return blks[i];
51 }
52 }
53 return 0;
54 }
55
56
57 void
58 SplitCacheSet::moveToHead(SplitBlk *blk)
59 {
60 // nothing to do if blk is already head
61 if (blks[0] == blk)
62 return;
63
64 // write 'next' block into blks[i], moving up from MRU toward LRU
65 // until we overwrite the block we moved to head.
66
67 // start by setting up to write 'blk' into blks[0]
68 int i = 0;
69 SplitBlk *next = blk;
70
71 do {
72 assert(i < assoc);
73 // swap blks[i] and next
74 SplitBlk *tmp = blks[i];
75 blks[i] = next;
76 next = tmp;
77 ++i;
78 } while (next != blk);
79 }
80
81
82 // create and initialize a LRU/MRU cache structure
83 SplitLRU::SplitLRU(int _numSets, int _blkSize, int _assoc, int _hit_latency, int _part) :
84 numSets(_numSets), blkSize(_blkSize), assoc(_assoc), hitLatency(_hit_latency), part(_part)
85 {
86 // Check parameters
87 if (blkSize < 4 || !isPowerOf2(blkSize)) {
88 fatal("Block size must be at least 4 and a power of 2");
89 }
90 if (numSets <= 0 || !isPowerOf2(numSets)) {
91 fatal("# of sets must be non-zero and a power of 2");
92 }
93 if (assoc <= 0) {
94 fatal("associativity must be greater than zero");
95 }
96 if (hitLatency <= 0) {
97 fatal("access latency must be greater than zero");
98 }
99
100 SplitBlk *blk;
101 int i, j, blkIndex;
102
103 blkMask = blkSize - 1;
104 setShift = floorLog2(blkSize);
105 setMask = numSets - 1;
106 tagShift = setShift + floorLog2(numSets);
107 warmedUp = false;
108 /** @todo Make warmup percentage a parameter. */
109 warmupBound = numSets * assoc;
110
111 sets = new SplitCacheSet[numSets];
112 blks = new SplitBlk[numSets * assoc];
113 // allocate data storage in one big chunk
114 dataBlks = new uint8_t[numSets*assoc*blkSize];
115
116 blkIndex = 0; // index into blks array
117 for (i = 0; i < numSets; ++i) {
118 sets[i].assoc = assoc;
119
120 sets[i].blks = new SplitBlk*[assoc];
121
122 // link in the data blocks
123 for (j = 0; j < assoc; ++j) {
124 // locate next cache block
125 blk = &blks[blkIndex];
126 blk->data = &dataBlks[blkSize*blkIndex];
127 ++blkIndex;
128
129 // invalidate new cache block
130 blk->status = 0;
131
132 //EGH Fix Me : do we need to initialize blk?
133
134 // Setting the tag to j is just to prevent long chains in the hash
135 // table; won't matter because the block is invalid
136 blk->tag = j;
137 blk->whenReady = 0;
138 blk->isTouched = false;
139 blk->size = blkSize;
140 sets[i].blks[j]=blk;
141 blk->set = i;
142 blk->part = part;
143 }
144 }
145 }
146
147 SplitLRU::~SplitLRU()
148 {
149 delete [] dataBlks;
150 delete [] blks;
151 delete [] sets;
152 }
153
154 void
155 SplitLRU::regStats(const std::string &name)
156 {
157 BaseTags::regStats(name);
158
159 hits
160 .name(name + ".hits")
161 .desc("number of hits on this partition")
162 .precision(0)
163 ;
164
165 misses
166 .name(name + ".misses")
167 .desc("number of misses in this partition")
168 .precision(0)
169 ;
170 }
171
172 // probe cache for presence of given block.
173 bool
174 SplitLRU::probe(Addr addr) const
175 {
176 // return(findBlock(Read, addr, asid) != 0);
177 Addr tag = extractTag(addr);
178 unsigned myset = extractSet(addr);
179
180 SplitBlk *blk = sets[myset].findBlk(tag);
181
182 return (blk != NULL); // true if in cache
183 }
184
185 SplitBlk*
186 SplitLRU::findBlock(Addr addr, int &lat)
187 {
188 Addr tag = extractTag(addr);
189 unsigned set = extractSet(addr);
190 SplitBlk *blk = sets[set].findBlk(tag);
191 lat = hitLatency;
192 if (blk != NULL) {
193 // move this block to head of the MRU list
194 sets[set].moveToHead(blk);
195 if (blk->whenReady > curTick && blk->whenReady - curTick > hitLatency){
196 lat = blk->whenReady - curTick;
197 }
198 blk->refCount += 1;
199 hits++;
200 }
201
202 return blk;
203 }
204
205 SplitBlk*
206 SplitLRU::findBlock(Packet * &pkt, int &lat)
207 {
208 Addr addr = pkt->getAddr();
209
210 Addr tag = extractTag(addr);
211 unsigned set = extractSet(addr);
212 SplitBlk *blk = sets[set].findBlk(tag);
213 lat = hitLatency;
214 if (blk != NULL) {
215 // move this block to head of the MRU list
216 sets[set].moveToHead(blk);
217 if (blk->whenReady > curTick && blk->whenReady - curTick > hitLatency){
218 lat = blk->whenReady - curTick;
219 }
220 blk->refCount += 1;
221 hits++;
222 }
223
224 return blk;
225 }
226
227 SplitBlk*
228 SplitLRU::findBlock(Addr addr) const
229 {
230 Addr tag = extractTag(addr);
231 unsigned set = extractSet(addr);
232 SplitBlk *blk = sets[set].findBlk(tag);
233 return blk;
234 }
235
236 SplitBlk*
237 SplitLRU::findReplacement(Packet * &pkt, PacketList &writebacks,
238 BlkList &compress_blocks)
239 {
240 unsigned set = extractSet(pkt->getAddr());
241 // grab a replacement candidate
242 SplitBlk *blk = sets[set].blks[assoc-1];
243 sets[set].moveToHead(blk);
244 if (blk->isValid()) {
245 replacements[0]++;
246 totalRefs += blk->refCount;
247 ++sampledRefs;
248 blk->refCount = 0;
249 } else if (!blk->isTouched) {
250 tagsInUse++;
251 blk->isTouched = true;
252 if (!warmedUp && tagsInUse.value() >= warmupBound) {
253 warmedUp = true;
254 warmupCycle = curTick;
255 }
256 }
257
258 misses++;
259
260 return blk;
261 }
262
263 void
264 SplitLRU::invalidateBlk(Addr addr)
265 {
266 SplitBlk *blk = findBlock(addr);
267 if (blk) {
268 blk->status = 0;
269 blk->isTouched = false;
270 tagsInUse--;
271 }
272 }
273
274 void
275 SplitLRU::doCopy(Addr source, Addr dest, PacketList &writebacks)
276 {
277 //Copy not supported for now
278 #if 0
279 assert(source == blkAlign(source));
280 assert(dest == blkAlign(dest));
281 SplitBlk *source_blk = findBlock(source);
282 assert(source_blk);
283 SplitBlk *dest_blk = findBlock(dest);
284 if (dest_blk == NULL) {
285 // Need to do a replacement
286 Packet * pkt = new Packet();
287 pkt->paddr = dest;
288 BlkList dummy_list;
289 dest_blk = findReplacement(pkt, writebacks, dummy_list);
290 if (dest_blk->isValid() && dest_blk->isModified()) {
291 // Need to writeback data.
292 pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag,
293 dest_blk->set),
294 dest_blk->xc,
295 blkSize,
296 (cache->doData())?dest_blk->data:0,
297 dest_blk->size);
298 writebacks.push_back(pkt);
299 }
300 dest_blk->tag = extractTag(dest);
301 /**
302 * @todo Do we need to pass in the execution context, or can we
303 * assume its the same?
304 */
305 assert(source_blk->xc);
306 dest_blk->xc = source_blk->xc;
307 }
308 /**
309 * @todo Can't assume the status once we have coherence on copies.
310 */
311
312 // Set this block as readable, writeable, and dirty.
313 dest_blk->status = 7;
314 if (cache->doData()) {
315 memcpy(dest_blk->data, source_blk->data, blkSize);
316 }
317 #endif
318 }
319
320 void
321 SplitLRU::cleanupRefs()
322 {
323 for (int i = 0; i < numSets*assoc; ++i) {
324 if (blks[i].isValid()) {
325 totalRefs += blks[i].refCount;
326 ++sampledRefs;
327 }
328 }
329 }